PDLXT310NE.D4 Intel, PDLXT310NE.D4 Datasheet - Page 10

• Manufacturer Part Number: PDLXT310NE.D4
• Manufacturer: Intel

Specifications of PDLXT310NE.D4

• Number Of Line Interfaces: 1
• Lead Free Status / Rohs Status: Not Compliant

LXT310 — T1 CSU/ISDN PRI Transceiver
2.3
2.3.1
10
RCLK
LATN
NOTE: LATN is stable and valid on the rising edge of RCLK
Figure 3. LATN Pulse Width Encoding
The equalized signal is filtered and applied to the peak detector and data slicers. The peak detector
samples the inputs and determines the maximum value of the received signal. A percentage of the
peak value is provided to the data slicers as a threshold level to ensure optimum signal-to-noise
ratio. The threshold is set to 50% of the peak value. The receiver is capable of accurately
recovering signals with up to 36 dB of cable attenuation (from 2.4 V)
After processing through the data slicers, the received signal is routed to the data and timing
recovery section, then to the B8ZS decoder (if selected) and to the LOS processor. The LOS
Processor loads a digital counter at the RCLK frequency. The count is incremented each time a
zero (space) is received, and reset to zero each time a one (mark) is received. Upon receipt of 175
consecutive zeros the LOS pin goes High, and a smooth transition replaces the RCLK output with
the MCLK. Note that during LOS, if MCLK is not supplied and JASEL = 1, the RCLK output is
replaced with the centered crystal clock.
Received marks will be output regardless of the LOS status, but the LOS pin will not reset until the
ones density reaches 12.5%. This level is based on receipt of at least 4 ones in any 32-bit period.
Transmitter
Input data (bipolar or unipolar) for transmission onto the line is clocked serially into the device.
Bipolar data is input at pin 3 (TPOS) and pin 4 (TNEG). Unipolar data is input at pin 3 (TDATA)
only. Unipolar mode is enabled by holding pin 4 high for 16 RCLK cycles. Input data may be
passed through the Jitter Attenuator and/or B8ZS encoder, if selected. In Host mode, B8ZS is
selected by setting bit D3 of the input data byte. In Hardware mode, B8ZS is selected by
connecting the MODE pin to RCLK. Input synchronization is supplied by the transmit clock
(TCLK). Timing requirements for TCLK and the Master Clock (MCLK) are defined in Test
Specifications.
Idle Mode
to a single line for redundant applications. TTIP and TRING remain in a high- impedance state
when TCLK is not present (TCLK grounded). The high-impedance state can be temporarily
disabled by enabling either TAOS, Remote Loopback or Network Loopback.
The LXT310 incorporates a transmit idle mode. This allows multiple transceivers to be connected
1
LATN = 1 RCLK, 7.5 dB of Attenuation
2
LATN = 2 RCLK, 15 dB of Attenuation
3
LATN = 3 RCLK, 22.5 dB of Attenuation
4
LATN = 4 RCLK, 0 dB of Attenuation
5
Datasheet