PDLXT310NE.D4 Intel, PDLXT310NE.D4 Datasheet - Page 11

• Manufacturer Part Number: PDLXT310NE.D4
• Manufacturer: Intel

Specifications of PDLXT310NE.D4

• Number Of Line Interfaces: 1
• Lead Free Status / Rohs Status: Not Compliant

2.3.2
2.3.3
2.4
Datasheet
Figure 4. 50% AMI Coding
The transmitted pulse shape is determined by Line Build Out (LBO) inputs LBO1 and LBO2 as
follows:
In Host mode, LBO is specified by setting the appropriate bits in the LXT310 register via the serial
port. In the Hardware mode, LBO inputs are applied through individual pins (1 = High; 0 = Low).
Shaped pulses meeting the various T1 CSU and ISDN PRI requirements are applied to the AMI
line driver for transmission onto the line at TTIP and TRING. Refer to Test Specifications for T1
pulse mask specifications.
Short Circuit Limit
The LXT310 transmitter is equipped with a short-circuit limiter. This feature limits to
approximately 120 mA RMS the current the transmitter will source into a low-impedance load.
The limiter trips when the RMS current exceeds the limit for 100 µs (~ 150 marks). It
automatically resets when the load current drops below the limit.
The LXT310 meets or exceeds FCC and AT&T specifications for CSU and NI applications, as well
as ANSI T1E1, and CCITT requirements for ISDN PRI.
Line Code
The LXT310 transmits data as a 50% AMI line code as shown in
reduced by activating the AMI line driver only to transmit a mark. The output driver is disabled
during transmission of a space. Biasing of the transmit DC level is on-chip.
Jitter Attenuation
Jitter attenuation is provided by a Jitter Attenuation Loop (JAL) and an Elastic Store (ES). An
external crystal oscillating at 4 times the bit rate provides clock stabilization. Refer to
crystal specifications. The ES is a 32 x 2-bit register. When JASEL = 1, the JAL is positioned in
the receive path. When JASEL = 0, the JAL is positioned in the transmit path.
Line Build-Out Control
LBO1
LBO2
TRING
TTIP
0
0
0
Bit Cell
7.5
1
0
1
dB
15
0
1
22.5
1
1
T1 CSU/ISDN PRI Transceiver — LXT310
0
Figure
1
4. Power consumption is
Table 6
for
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