PDLXT310NE.D4 Intel, PDLXT310NE.D4 Datasheet - Page 23

• Manufacturer Part Number: PDLXT310NE.D4
• Manufacturer: Intel

Specifications of PDLXT310NE.D4

• Number Of Line Interfaces: 1
• Lead Free Status / Rohs Status: Not Compliant

Datasheet
Master clock frequency
Master clock tolerance
Master clock duty cycle
Crystal frequency
Transmit clock frequency
Transmit clock tolerance
Transmit clock duty cycle
TPOS/TNEG to TCLK setup time
TCLK to TPOS/TNEG hold time
Rise/Fall time - any digital output
SDI to SCLK setup time
SCLK to SDI hold time
SCLK low time
SCLK high time
SCLK rise and fall time
CS to SCLK setup time
SCLK to CS hold time
CS inactive time
SCLK to SDO valid
SCLK falling edge or CS rising edge
to SDO high Z
1. Typical values are at 25 °C and are for design aid only; they are not guaranteed and not subject to production testing.
1. Typical values are at 25° C and are for design aid only; they are not guaranteed and not subject to production testing.
Table 13. LXT310 Master Clock and Transmit Timing Characteristics (See Figure 11)
Figure 11. LXT310 Transmit Clock Timing Diagram
Table 14. LXT310 Serial I/O Timing Characteristics (See Figure 12 and Figure 13)
Parameter
Parameter
TPOS
TNEG
TCLK
t
t
MCLKd
Sym
t
t
TCLKd
t
t
MCLKt
TCLKt
R
CWH
MCLK
t
CDH
t
t
CCH
CDV
TCLK
t
t
CDZ
Sym
DC
CH
CC
RF
CL
t
, t
SUT
t
fc
HT
F
Min
240
240
250
50
50
50
50
–
–
–
–
t
Min
40
10
50
50
SUT
–
–
–
–
–
Typ
100
–
–
–
–
–
–
–
–
–
–
1
1.544
6.176
1.544
Typ
±100
T1 CSU/ISDN PRI Transceiver — LXT310
Max
–
–
–
–
–
t
100
200
HT
50
–
–
–
–
–
–
–
–
1
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
±100
Max
60
90
–
–
–
–
–
–
Load 1.6 mA, 50 pF
Units
MHz
MHz
MHz
ppm
ppm
Test Conditions
ns
ns
%
%
LXT310 only
Notes
23