PDLXT310NE.D4 Intel, PDLXT310NE.D4 Datasheet - Page 22

• Manufacturer Part Number: PDLXT310NE.D4
• Manufacturer: Intel

Specifications of PDLXT310NE.D4

• Number Of Line Interfaces: 1
• Lead Free Status / Rohs Status: Not Compliant

LXT310 — T1 CSU/ISDN PRI Transceiver
22
Receive clock duty cycle
Receive clock period
Receive clock pulse width high
Receive clock pulse width low
RPOS/RNEG to RCLK rising setup time
RCLK rising to RPOS/RNEG hold time
1. Typical values are at 25 °C and are for design aid only; they are not guaranteed and not subject to production testing.
2. RCLK duty cycle widths will vary depending on extent of received pulse jitter displacement. Max and Min RCLK duty cycles
are for worst case jitter conditions (0.4 UI clock displacement for 1.544 MHz).
Table 11. Pulse Mask Corner Point Specifications
Table 12. LXT310 Receive Timing Characteristics (See Figure 10)
Figure 10. LXT310 Receive Clock Timing Diagram
Time (ns)
1100
1250
425
500
675
725
RNEG
RNEG
RPOS
RPOS
RCLK
Maximum Curve
2
Parameter
t
t
PWL
SUR
% V
105
120
105
t
5
5
5
PW
t
t
PWH
SUR
t
HR
RCLKd
t
Sym
t
t
t
PWH
PWL
SUR
t
t
PW
HR
HR
Time (ns)
1250
1100
500
600
650
650
800
896
Min
600
303
40
–
–
–
Minimum Curve
Host mode
CLKE = 1
Host mode
CLKE = 0, &
H/W mode
Typ
648
324
324
274
274
50
1
Max
700
345
60
–
–
–
% V
-45
-45
-26
95
90
50
-5
-5
Datasheet
Units
ns
ns
ns
ns
ns
%