PDLXT310NE.D4 Intel, PDLXT310NE.D4 Datasheet - Page 18

• Manufacturer Part Number: PDLXT310NE.D4
• Manufacturer: Intel

Specifications of PDLXT310NE.D4

• Number Of Line Interfaces: 1
• Lead Free Status / Rohs Status: Not Compliant

LXT310 — T1 CSU/ISDN PRI Transceiver
3.2
18
2.048 MHz
NOTE: The LXT310 is compatible
Figure 7. Typical LXT310 Host Mode T1/CSU Application
with a wide variety of framing/
signaling devices
CLKO
LXP600A CLAD
LXT310 Hardware Mode Applications
Figure 8
LXP600A clock adapter. The LXT310 is operating in the Hardware mode with B8ZS encoding
enabled (MODE pin 5 tied to RCLK). As in the T1/CSU application,
illustrated with a single power supply bus. CMOS control logic is used to set both LBO pins high,
TMSYNC
CS
SDO
SDI
INT
SCLK
FRAMER
See Note 1
T1/ESF
is a typical 1.544 Mbps ISDN PRI application with the LXT310, a T1/ESF framer and an
CLKI
FSI
FSYNC
RNEG
RPOS
TNEG
TPOS
RCLK
TCLK
SPS
1.544
MHz
To Host Controller
V+
6.176
MHz
1.544
MHz
MCLK
TCLK
TPOS
TNEG
MODE
RNEG
RPOS
RCLK
XTALIN
XTALOUT
JASEL
LOS
TTIP
TGND
TRANSCEIVER
1.0 F
LXT310
RRING
TRING
RGND
68 F
CLKE
SCLK
LATN
RTIP
SDO
RV+
EGL
TV+
SDI
INT
CS
Figure
0V
100
0.1 F
7, this configuration is
12.5
12.5
See
Figure 6
V+
Figure 3
1:1
1:2
Datasheet
22 k
V+
T1 Line
Receive
1.544 MHz
T1 Line
Transmit
&