PDLXT310NE.D4 Intel, PDLXT310NE.D4 Datasheet - Page 12

• Manufacturer Part Number: PDLXT310NE.D4
• Manufacturer: Intel

Specifications of PDLXT310NE.D4

• Number Of Line Interfaces: 1
• Lead Free Status / Rohs Status: Not Compliant

LXT310 — T1 CSU/ISDN PRI Transceiver
2.5
2.5.1
12
Table 2.
Data (TPOS/TNEG / TDATA or RPOS/RNEG / RDATA) is clocked into the ES with the associated
clock signal (TCLK or RCLK), and clocked out of the ES with the dejittered clock from the JAL.
When the bit count in the ES is within two bits of overflowing or underflowing, the ES adjusts the
output clock by 1/8 of a bit period. The ES produces an average delay of 16 bits in the associated
path.
Operating Modes
The LXT310 can be controlled by a microprocessor through a serial interface (Host mode), or
through individual pins (Hardware mode). The mode of operation is set by the MODE pin logic
level.
Host Mode Operation
The LXT310 operates in the Host mode when MODE is set High. The 16-bit serial word consists
of an 8-bit Command/Address byte and an 8-bit Data byte.
Table 3
timing. The Host mode provides a latched Interrupt output (INT) which is triggered by a change in
the LOS or NLOOP bits. The Interrupt is cleared when the interrupt condition no longer exists,
and the host processor writes a one to the respective bit in the serial input data byte.
Host mode also allows control of the serial data and receive data output timing. The Clock Edge
(CLKE) signal determines when these outputs are valid, relative to the Serial Clock (SCLK) or
RCLK as listed in
CLKE Settings
The LXT310 serial port is addressed by setting bit A4 in the Address/Command byte,
corresponding to address 16. The LXT310 contains only a single output data register so no
complex chip addressing scheme is required. The register is accessed by causing the Chip Select
(CS) input to transition from High to Low. Bit 1 of the serial Address/Command byte provides
Read/Write control when the chip is accessed. A logic 1 indicates a read operation, and a logic 0
indicates a write operation. Serial data I/O timing characteristics are shown in
12
RPOS/RNEG
and
Output
SDO
Figure 13
lists the output data bit combinations.
in the Test Specifications section.
Table
Clock
RCLK
SCLK
2.
CLKE = 0
Falling
Rising
Figure 5
CLKE = 1
Falling
Rising
shows the serial interface data structure and
Table
14, and
Datasheet
Figure