PDLXT310NE.D4 Intel, PDLXT310NE.D4 Datasheet - Page 8

• Manufacturer Part Number: PDLXT310NE.D4
• Manufacturer: Intel

Specifications of PDLXT310NE.D4

• Number Of Line Interfaces: 1
• Lead Free Status / Rohs Status: Not Compliant

LXT310 — T1 CSU/ISDN PRI Transceiver
8
Pin #
19
20
21
22
23
24
25
26
27
28
Table 1.
NLOOP
RLOOP
LLOOP
RRING
RGND
LBO1
LBO2
SCLK
CLKE
TAOS
RTIP
SDO
Sym
RV+
INT
SDI
CS
Pin Descriptions (Continued)
I/O
O
O
O
–
–
I
I
I
I
I
I
I
I
I
I
I
Receive Tip; Receive Ring. The AMI signal received from the line is applied at these pins.
A 1:1 transformer is required. Data and clock from the signal applied at these pins are
recovered and output on the RPOS/RNEG and RCLK pins.
Receive Power Supply. +5 VDC power supply for all circuits except the transmit drivers.
(Transmit drivers are supplied by TV+.)
Receive Ground. Ground return for power supply RV+.
Network Loopback (H/W mode). When High, indicates Inband Network Loopback has been
activated by reception of 00001 pattern for five seconds. NLOOP is reset by reception of 001
for five seconds, or by activation of RLOOP or LLOOP.
Interrupt (Host mode). In Host mode INT goes Low to flag the host processor when LOS or
NLOOP changes state. INT is an open-drain output and should be tied to power supply RV+
through a resistor. INT is reset by clearing the LOS or NLOOP register bit.
Serial Data In (Host mode). The serial data input stream is applied to this pin when the
LXT310 operates in the Host mode. SDI is sampled on the rising edge of SCLK.
Line Build-Out Select 1 (H/W mode). In Hardware mode LBO1 works in conjunction with
LBO2 to select the transmit line build-outs: 00 = 0 dB, 01 = 7.5 dB, 10 = 15 dB, and 11 = 22.5
dB.
Serial Data Out (Host mode). The serial data from the LXT310 register is output on this pin
in Host mode. If CLKE is High, SDO is valid on the rising edge of SCLK. If CLKE is Low,
SDO is valid on the falling edge of SCLK. This pin goes to a high-impedance state when the
serial port is being written to and when CS is High.
Line Build-Out Select 2 (H/W mode). Refer to LBO1 signal description.
Chip Select (Host mode). This pin selects the serial interface in the Host mode. For each
read or write operation, CS must transition from High to Low, and remain Low.
Remote Loopback (H/W mode). This pin controls loopback in the Hardware mode. Setting
RLOOP High enables Remote Loopback. During Remote Loopback, in-line encoders and
decoders are bypassed. Setting both RLOOP and LLOOP High, while holding TAOS Low,
causes a Reset. Setting both RLOOP and LLOOP High, with TAOS High (or tying RCLK to
RLOOP), enables Network Loopback detection.
Serial Clock (Host mode). This clock is used in the Host mode to write data to or read data
from the serial interface registers.
Local Loopback (H/W mode). This input controls loopback functions in the Hardware mode.
Setting LLOOP High enables the Local Loopback mode. Setting both LLOOP and RLOOP
High, while holding TAOS Low, causes a Reset.
Clock Edge Select (Host mode). Setting CLKE High causes RPOS and RNEG to be valid
on the falling edge of RCLK, and SDO to be valid on the rising edge of SCLK. When CLKE is
Low, RPOS and RNEG are valid on the rising edge of RCLK, and SDO is valid on the falling
edge of SCLK.
Transmit All Ones (H/W mode). When set High in the Hardware mode, TAOS causes the
LXT310 to transmit a stream of marks at the TCLK frequency. Activating TAOS causes
TPOS and TNEG inputs to be ignored. TAOS is inhibited during Remote Loopback. Setting
TAOS, LLOOP and RLOOP High simultaneously enables Network Loopback detection.
Description
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