PDLXT310NE.D4 Intel, PDLXT310NE.D4 Datasheet - Page 5

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PDLXT310NE.D4

Manufacturer Part Number
PDLXT310NE.D4
Description
Manufacturer
Intel
Datasheet

Specifications of PDLXT310NE.D4

Number Of Line Interfaces
1
Lead Free Status / Rohs Status
Not Compliant
Datasheet
Figure 1. LXT310 Block Diagram
XTAL OUT
XTAL IN
NLOOP
JASEL
RPOS
RNEG
TNEG
TPOS
RCLK
TCLK
LOS
INT
Decoder
Encoder
Enable
Enable
Unipolar
Decoder
B8ZS/
Unipolar
Encoder
B8ZS/
RLOOP
Enable
Loopback
Remote
Inband NLOOP &
LOS Processor
Jitter Attenuator
Serial Word
Enable
Transmit
Timing &
TAOS
Control
Receive Clock
LOS/
NLOOP
Clear
Generator
Timing and
Recovery
Data
Atten & Filter
Select
Transmit
LBO
(LBO)
Slicers
& Peak Detectors
T1 CSU/ISDN PRI Transceiver — LXT310
LLOOP Enable
Equalizer
Control
Crosstalk
Noise &
Filter
Serial
Port
Line Drivers
Gain
Equalizer
Receive
Loopback
Local
CLKE
CS
SCLK
SDI
SDO
TTIP
TRING
LATN
EGL
RTIP
RRING
MCLK
5

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