PSF21150HV14NP Infineon Technologies, PSF21150HV14NP Datasheet - Page 244
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PSF21150HV14NP
Manufacturer Part Number
PSF21150HV14NP
Description
Manufacturer
Infineon Technologies
Datasheet
1.PSF21150HV14NP.pdf
(270 pages)
Specifications of PSF21150HV14NP
Number Of Line Interfaces
1
Control Interface
HDLC
Lead Free Status / Rohs Status
Not Compliant
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Note: Min. value in synchronous state, max. value in non-synchronous state. This
DCL Clock Output Characteristics
Figure 93
Symbol
t
t
t
DCL Clock Input Characteristics
Parameter
Duty cycle
Data Sheet
P
WH
WL
results in a phase shift of FSC when the S-Bus gets activated, this is the FSC
signal is shifted by 135 ns. This applies only to TE mode.
2.3 V
Definition of Clock Period and Width
min.
585
260
260
Limit Values
typ.
651
325
325
max.
717
391
391
244
min.
40
Unit
ns
ns
ns
Limit Values
Electrical Characteristics
max.
60
Test Condition
osc
osc
osc
±
±
±
100 ppm
100 ppm
100 ppm
PSB/PSF 21150
Unit
%
2003-01-30
IPAC-X
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