CYP15G0401DXB-BGC Cypress Semiconductor Corp, CYP15G0401DXB-BGC Datasheet - Page 12

• Manufacturer Part Number: CYP15G0401DXB-BGC
• Description: IC TXRX HOTLINK 256LBGA
• Manufacturer: Cypress Semiconductor Corp
• Series: HOTlink II™r
• Type: Transceiverr

Specifications of CYP15G0401DXB-BGC

• Package / Case: 256-LBGA Exposed Pad, 32-HLBGA
• Number Of Drivers/receivers: 4/4
• Protocol: Multiprotocol
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Product: PHY
• Supply Voltage (min): 3.135 V
• Supply Current: 1.06 A
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Channels: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CYP15G0401DX-EVAL - IC TXRX HOTLINK 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Document #: 38-02002 Rev. *L
Pin Descriptions
CYP(V)(W)15G0401DXB Quad HOTLink II Transceiver
DECMODE
RFMODE
PARCTL
SPDSEL
TRSTZ
Device Control Signals
Pin Name
Three-level Select
static control input
Three-level Select
static control input
Three-level Select
static control input
Three-level Select
static control input
LVTTL Input,
internal pull-up
I/O Characteristics
(continued)
[5]
[5]
[5]
[5]
,
,
,
Decoder Mode Select. This input selects the behavior of the Decoder block. When
LOW, the Decoder is bypassed and raw 10-bit characters are passed to the Output
Register. When the Decoder is bypassed, RXCKSEL must be MID.
When MID, the Decoder is enabled and the Cypress decoder table for Special Code
characters is used.
When HIGH, the Decoder is enabled and the alternate decoder table for Special Code
characters is used. See Table 29 for a list of the Special Codes supported in both
encoded modes.
Reframe Mode Select. Used to select the type of character framing used to adjust
the character boundaries (based on detection of one or more framing characters in
the received serial bit stream). This signal operates in conjunction with the presently
enabled channel bonding mode, and the type of framing character selected.
When LOW, the Low-Latency Framer is selected. This will frame on each occurrence
of the selected framing character(s) in the received data stream. This mode of framing
stretches the recovered character-rate clock for one or multiple cycles to align that
clock with the recovered data.
When MID, the Cypress-mode Multi-Byte parallel Framer is selected. This requires a
pair of the selected framing character(s), on identical 10-bit boundaries, within a span
of 50 bits, before the character boundaries are adjusted. The recovered character
clock remains in the same phase regardless of character offset.
When HIGH, the alternate mode Multi-Byte parallel Framer is selected. This requires
detection of the selected framing character(s) of the allowed disparities in the received
serial bit stream, on identical 10-bit boundaries, on four directly adjacent characters.
The recovered character clock remains in the same phase regardless of character
offset.
Parity Check/Generate Control. Used to control the different parity check and
generate functions. When LOW, parity checking is disabled, and the RXOPx outputs
are all disabled (High-Z). When MID, and the 8B/10B Encoder and Decoder are
enabled (TXMODE[1] ≠ LOW, DECMODE ≠ LOW), TXDx[7:0] inputs are checked
(along with TXOPx) for valid ODD parity, and ODD parity is generated for the
RXDx[7:0] outputs and presented on RXOPx. When the Encoder and Decoder are
disabled (TXMODE[1] = LOW, DECMODE = LOW), theTXDx[7:0] and TXCTx[1:0]
inputs are checked (along with TXOPx) for valid ODD parity, and ODD parity is
generated for the RXDx[7:0] and RXSTx[1:0] outputs and presented on RXOPx. When
HIGH, parity checking and generation are enabled. The TXDx[7:0] and TXCTx[1:0]
inputs are checked (along with TXOPx) for valid ODD parity, and ODD parity is
generated for the RXDx[7:0] and RXSTx[2:0] outputs and presented on RXOPx. See
Table 2 and 19 for details.
Serial Rate Select. This input specifies the operating bit-rate range of both transmit
and receive PLLs. LOW = 195–400 MBaud, MID = 400–800 MBaud,
HIGH = 800–1500 MBaud (800–1540 MBaud for CYW15G0401DXB). When SPDSEL
is LOW, setting TXRATE = HIGH (Half-rate Reference Clock) is invalid.
Device Reset. Active LOW. Initializes all state machines and counters in the device.
When sampled LOW by the rising edge of REFCLK↑, this input resets the internal
state machines and sets the Elasticity Buffer pointers to a nominal offset. When the
reset is removed (TRSTZ sampled HIGH by REFCLK↑), the status and data outputs
will become deterministic in less than 16 REFCLK cycles. The BISTLE, OELE, and
RXLE latches are reset by TRSTZ. If the Elasticity Buffer or the Phase-align Buffer
are used, TRSTZ should be applied after power up to initialize the internal pointers
into these memory arrays.
Signal Description
CYW15G0401DXB
CYP15G0401DXB
CYV15G0401DXB
Page 12 of 53