CYP15G0401DXB-BGC Cypress Semiconductor Corp, CYP15G0401DXB-BGC Datasheet - Page 13

• Manufacturer Part Number: CYP15G0401DXB-BGC
• Description: IC TXRX HOTLINK 256LBGA
• Manufacturer: Cypress Semiconductor Corp
• Series: HOTlink II™r
• Type: Transceiverr

Specifications of CYP15G0401DXB-BGC

• Package / Case: 256-LBGA Exposed Pad, 32-HLBGA
• Number Of Drivers/receivers: 4/4
• Protocol: Multiprotocol
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Product: PHY
• Supply Voltage (min): 3.135 V
• Supply Current: 1.06 A
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Channels: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CYP15G0401DX-EVAL - IC TXRX HOTLINK 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Document #: 38-02002 Rev. *L
Pin Descriptions
CYP(V)(W)15G0401DXB Quad HOTLink II Transceiver
REFCLK±
OUTA1±
OUTB1±
OUTC1±
OUTD1±
OUTA2±
OUTB2±
OUTC2±
OUTD2±
INA1±
INB1±
INC1±
IND1±
INA2±
INB2±
INC2±
IND2±
INSELA
INSELB
INSELC
INSELD
SDASEL
LPEN
OELE
Analog I/O and Control
Pin Name
Differential LVPECL or
single-ended
LVTTL Input Clock
CML Differential
Output
CML Differential
Output
LVPECL Differential Input Primary Differential Serial Data Inputs. These inputs accept the serial data stream
LVPECL Differential Input Secondary Differential Serial Data Inputs. These inputs accept the serial data
LVTTL Input,
asynchronous
Three-level Select
static configuration input
LVTTL Input,
asynchronous,
internal pull-down
LVTTL Input,
asynchronous,
internal pull-up
I/O Characteristics
(continued)
[5]
Reference Clock. This clock input is used as the timing reference for the transmit
PLL. It is also used as the centering frequency of the Range Controller block of the
Receive CDR PLLs.This input clock may also be selected to clock the transmit and
receive parallel interfaces. When driven by a single-ended LVCMOS or LVTTL clock
source, connect the clock source to either the true or complement REFCLK input, and
leave the alternate REFCLK input open (floating). When driven by an LVPECL clock
source, the clock must be a differential clock, using both inputs. When TXCKSEL =
LOW, REFCLK is also used as the clock for the parallel transmit data (input) interface.
When RXCKSEL = LOW, the Elasticity Buffer is enabled and REFCLK is used as the
clock for the parallel receive data (output) interface.
If the Elasticity Buffer is used, framing characters will be inserted or deleted to/from
the data stream to compensate for frequency differences between the reference clock
and recovered clock. When an addition happens, a K28.5 will be appended immedi-
ately after a framing is detected in the Elasticity Buffer. When deletion happens, a
framing character will be removed from the data stream when detected in the Elasticity
Buffer.
Primary Differential Serial Data Outputs. These PECL-compatible CML outputs
(+3.3V referenced) are capable of driving terminated transmission lines or standard
fiber-optic transmitter modules.
Secondary Differential Serial Data Outputs. These PECL-compatible CML outputs
(+3.3V referenced) are capable of driving terminated transmission lines or standard
fiber-optic transmitter modules.
for deserialization and decoding. The INx1± serial streams are passed to the receiver
Clock and Data Recovery (CDR) circuits to extract the data content when INSELx =
HIGH.
stream for deserialization and decoding. The INx2± serial streams are passed to the
receiver Clock and Data Recovery (CDR) circuits to extract the data content when
INSELx = LOW.
Receive Input Selector. Determines which external serial bit stream is passed to the
receiver Clock and Data Recovery circuit. When HIGH, the INx1± input is selected.
When LOW, the INx2± input is selected.
Signal Detect Amplitude Level Select. Allows selection of one of three predefined
amplitude trip points for a valid signal indication, as listed in Table 12.
All-Port Loop-Back Enable. Active HIGH. When asserted (HIGH), the transmit serial
data from each channel is internally routed to the associated receiver Clock and Data
Recovery (CAR) circuit. All enabled serial drivers are forced to differential logic “1.”
All serial data inputs are ignored.
Serial Driver Output Enable Latch Enable. Active HIGH. When OELE = HIGH, the
signals on the BOE[7:0] inputs directly control the OUTxy± differential drivers. When
the BOE[x] input is HIGH, the associated OUTxy± differential driver is enabled. When
the BOE[x] input is LOW, the associated OUTxy± differential driver is powered down.
The specific mapping of BOE[7:0] signals to transmit output enables is listed in
Table 10. When OELE returns LOW, the last values present on BOE[7:0] are captured
in the internal Output Enable Latch. If the device is reset (TRSTZ is sampled LOW),
the latch is reset to disable all outputs.
Signal Description
CYW15G0401DXB
CYP15G0401DXB
CYV15G0401DXB
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