CYP15G0401DXB-BGC Cypress Semiconductor Corp, CYP15G0401DXB-BGC Datasheet - Page 28

• Manufacturer Part Number: CYP15G0401DXB-BGC
• Description: IC TXRX HOTLINK 256LBGA
• Manufacturer: Cypress Semiconductor Corp
• Series: HOTlink II™r
• Type: Transceiverr

Specifications of CYP15G0401DXB-BGC

• Package / Case: 256-LBGA Exposed Pad, 32-HLBGA
• Number Of Drivers/receivers: 4/4
• Protocol: Multiprotocol
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Product: PHY
• Supply Voltage (min): 3.135 V
• Supply Current: 1.06 A
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Channels: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CYP15G0401DX-EVAL - IC TXRX HOTLINK 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Document #: 38-02002 Rev. *L
.
Table 18. Decoder Bypass Mode (DECMODE = LOW)
When the Cypress or Alternate Mode Framer is enabled and
half-rate
(RFMODE ≠ LOW and RXRATE = HIGH), the output clock is
not modified when framing is detected, but a single pipeline
stage may be added or subtracted from the data stream by the
Framer logic such that the rising edge of RXCLKx+ occurs
when COMDETx is present on the associated output bus.
This adjustment only occurs when the Framer is enabled
(RFEN = HIGH). When the Framer is disabled, the clock
boundaries are not adjusted, and COMDETx may be asserted
during the rising edge of RXCLK– (if an odd number of
characters were received following the initial framing).
Parity Generation
In addition to the eleven data and status bits that are presented
by each channel, an RXOPx parity output is also available on
each channel. This allows the CYP(V)(W)15G0401DXB to
support ODD parity generation for each channel. To handle a
wide
CYP(V)(W)15G0401DXB supports different forms of parity
generation, including no parity.
When the decoders are enabled (DECMODE ≠ LOW), parity
can be generated on
When the decoders are bypassed (DECMODE = LOW), parity
can be generated on
These modes differ in the number of bits which are included in
the parity calculation. Only ODD parity is provided which
ensures that at least one bit of the data bus is always a logic-1.
Those bits covered by parity generation are listed in Table 19.
Parity generation is enabled through the three-level select
PARCTL input. When PARCTL = LOW, parity checking is
disabled, and the RXOPx outputs are all disabled (High-Z).
When PARCTL = MID (open) and the decoders are enabled
(DECMODE ≠ LOW), ODD parity is generated for the received
Notes:
19. Receive path parity output drivers (RXOPx) are disabled (High-Z) when PARCTL = LOW.
20. When the Decoder is bypassed (DECMODE = LOW) and BIST is not enabled (Receive BIST Latch output is HIGH), RXSTx[2] is driven to a logic-0, except
• the RXDx[7:0] character
• the RXDx[7:0] character and RXSTx[2:0] status.
• the RXDx[7:0] and RXSTx[1:0] bits
• the RXDx[7:0] and RXSTx[2:0] bits.
RXSTx[2]
RXDx[7]
Signal Name
when the character in the output buffer is a framing character.
RXSTx[1]
RXSTx[0]
RXDx[0]
RXDx[1]
RXDx[2]
RXDx[3]
RXDx[4]
RXDx[5]
RXDx[6]
range
receive
(MSB)
(LSB)
of
port
Bus Weight
COMDETx
system
2
2
2
2
2
2
2
2
2
2
clocking
0
1
2
3
4
5
6
7
8
9
environments,
is
10Bit Name
also
a
b
d
e
g
h
c
f
i
j
enabled
the
Table 19. Output Register Parity Generation
and decoded character in the RXDx[7:0] signals and is
presented
PARCTL = MID
(DECMODE = LOW), ODD parity is generated for the received
and decoded character in the RXDx[7:0] and RXSTx[1:0] bit
positions. When PARCTL = HIGH, ODD parity is generated for
the RXDx[7:0] and the associated RXSTx[2:0] status bits.
Receive Status Bits
When the 10B/8B Decoder is enabled (DECMODE ≠ LOW),
each character presented at the Output Register includes
three associated status bits. These bits are used to identify:
These conditions normally overlap; e.g., a valid data character
received with incorrect running disparity is not reported as a
valid data character. It is instead reported as a Decoder
violation of some specific type. This implies a hierarchy or
priority level to the various status bit combinations. The
hierarchy and value of each status is listed in Table 20 when
channel bonding enabled and in Table 23 when channel
bonding is disabled.
Within these status codes, there are three modes of status
reporting. The two data status reporting modes (Type A and
Type B) are selectable through the RXMODE[0] input. These
status types allow compatibility with legacy systems, while
allowing full reporting in new systems. These status values are
generated in part by the Receive Synchronization State
Machine, and are listed in Table 20. The receive status when
the channels are operated independently with channel
bonding disabled is shown in Table 23. The receive status
when Receive BIST is enabled is shown in Table 24.
• if the contents of the data bus are valid
• the type of character present
• the state of receive BIST operations (regardless of the state
• character violations
• channel bonding status.
RXSTx[2]
RXSTx[1]
RXSTx[0]
RXDx[0]
RXDx[1]
RXDx[2]
RXDx[3]
RXDx[4]
RXDx[5]
RXDx[6]
RXDx[7]
of DECMODE)
Signal
Name
on
Receive Parity Generate Mode (PARCTL)
LOW
[19]
the
and
associated
DECMODE
the
= LOW
X
X
X
X
X
X
X
X
X
X
CYW15G0401DXB
CYP15G0401DXB
CYV15G0401DXB
decoders
MID
RXOPx
DECMODE
≠ LOW
X
X
X
X
X
X
X
X
are
output. When
Page 28 of 53
bypassed
HIGH
X
X
X
X
X
X
X
X
X
X
X
[20]