CYP15G0401DXB-BGC Cypress Semiconductor Corp, CYP15G0401DXB-BGC Datasheet - Page 9

• Manufacturer Part Number: CYP15G0401DXB-BGC
• Description: IC TXRX HOTLINK 256LBGA
• Manufacturer: Cypress Semiconductor Corp
• Series: HOTlink II™r
• Type: Transceiverr

Specifications of CYP15G0401DXB-BGC

• Package / Case: 256-LBGA Exposed Pad, 32-HLBGA
• Number Of Drivers/receivers: 4/4
• Protocol: Multiprotocol
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Product: PHY
• Supply Voltage (min): 3.135 V
• Supply Current: 1.06 A
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Channels: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CYP15G0401DX-EVAL - IC TXRX HOTLINK 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Document #: 38-02002 Rev. *L
Pin Descriptions
CYP(V)(W)15G0401DXB Quad HOTLink II Transceiver
TXRST
Transmit Path Clock and Clock Control
TXCKSEL
TXCLKO±
TXRATE
TXCLKA
TXCLKB
TXCLKC
TXCLKD
Note:
5.
Pin Name
Three-level select inputs are used for static configuration. They are ternary (not binary) inputs that make use of non-standard logic levels of LOW, MID, and
HIGH. The LOW level is usually implemented by direct connection to V
not connected or allowed to float, a Three-level select input will self-bias to the MID level.
LVTTL Input,
asynchronous,
internal pull-up,
sampled by
REFCLK↑
Three-level Select
static control input
LVTTL Output
LVTTL Input,
static control input,
internal pull-down
LVTTL Clock Input,
internal
pull-down
I/O Characteristics
(continued)
[4]
[5]
,
Transmit Clock Phase Reset. Active LOW. When sampled LOW, the transmit
Phase-align Buffers are allowed to adjust their data-transfer timing (relative to the
selected input clock) to allow clean transfer of data from the Input Register to the
Encoder or Transmit Shifter. When TXRST is sampled HIGH, the internal phase
relationship between the associated TXCLKx and the internal character-rate clock is
fixed and the device operates normally.
When configured for half-rate REFCLK sampling of the transmit character stream
(TXCKSEL = LOW and TXRATE = HIGH), assertion of TXRST is only used to clear
Phase-align buffer faults caused by highly asymmetric REFCLK periods or REFCLKs
with excessive cycle-to-cycle jitter. During this alignment period, one or more
characters may be added to or lost from all the associated transmit paths as the
transmit Phase-align Buffers are adjusted. TXRST must be sampled LOW by a
minimum of two consecutive rising edges REFCLK to ensure the reset operation is
initiated correctly on all channels. This input is ignored when both TXCKSEL and
TXRATE are LOW, since the phase align buffer is bypassed. In all other configurations,
TXRST should be asserted during device initialization to ensure proper operation of
the Phase-align buffer. TXRST should be asserted after the presence of a valid
TXCLKx and after allowing enough time for the TXPLL to lock to the reference clock
(as specified by parameter t
Transmit Clock Select. Selects the clock source, used to write data into the transmit
Input Register of the transmit channel(s). When LOW, REFCLK↑
Input Register clock for TXDx[7:0] and TXCTx[1:0] of all channels. When MID,
TXCLKx↑ is used as the Input Register clock for TXDx[7:0] and TXCTx[1:0]. When
HIGH, TXCLKA↑ is used as the Input Register clock for TXDx[7:0] and TXCTx[1:0] of
all channels.
Transmit Clock Output. This true and complement output clock is synthesized by
the transmit PLL and is synchronous to the internal transmit character clock. It has
the same frequency as REFCLK (when TXRATE = LOW), or twice the frequency of
REFCLK (when TXRATE = HIGH). This output clock has no direct phase relationship
to REFCLK.
Transmit PLL Clock Rate Select. When TXRATE = HIGH, the Transmit PLL multi-
plies REFCLK by 20 to generate the serial bit-rate clock. When TXRATE = LOW, the
transmit PLL multiples REFCLK by 10 to generate the serial bit-rate clock. See
Table 11 for a list of operating serial rates.
When REFCLK is selected to clock the receive parallel interfaces (RXCKSEL = LOW),
the TXRATE input also determines if the clocks on the RXCLKA± and RXCLKC±
outputs are full or half-rate. When TXRATE = HIGH (REFCLK is half-rate), the
RXCLKA± and RXCLKC± output clocks are also half-rate clocks and follow the
frequency and duty cycle of the REFCLK input. When TXRATE = LOW (REFCLK is
full-rate), the RXCLKA± and RXCLKC± output clocks are full-rate clocks and follow
the frequency and duty cycle of the REFCLK input.
When TXCKSEL = MID or HIGH (TXCLKx or TXCLKA selected to clock input
register), configuring TXRATE = HIGH (Half-rate REFCLK) is an invalid mode of
operation.
Transmit Path Input Clocks. These clocks must be frequency-coherent to
TXCLKO±, but may be offset in phase. The internal operating phase of each input
clock (relative to REFLCK or TXCLKO±) is adjusted when TXRST = LOW and locked
when TXRST = HIGH.
SS
(ground). The HIGH level is usually implemented by direct connection to V
TXLOCK
Signal Description
).
CYW15G0401DXB
CYP15G0401DXB
CYV15G0401DXB
[4]
is used as the
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CC
. When