CYP15G0401DXB-BGC Cypress Semiconductor Corp, CYP15G0401DXB-BGC Datasheet - Page 25

• Manufacturer Part Number: CYP15G0401DXB-BGC
• Description: IC TXRX HOTLINK 256LBGA
• Manufacturer: Cypress Semiconductor Corp
• Series: HOTlink II™r
• Type: Transceiverr

Specifications of CYP15G0401DXB-BGC

• Package / Case: 256-LBGA Exposed Pad, 32-HLBGA
• Number Of Drivers/receivers: 4/4
• Protocol: Multiprotocol
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Product: PHY
• Supply Voltage (min): 3.135 V
• Supply Current: 1.06 A
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Channels: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CYP15G0401DX-EVAL - IC TXRX HOTLINK 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Document #: 38-02002 Rev. *L
The BIST state machine requires the characters to be correctly
framed for it to detect the BIST sequence. If the Low Latency
Framer is enabled (RFMODE = LOW), the Framer will
misalign to an aliased framing character within the BIST
sequence. If the Alternate Multi-Byte Framer is enabled
(RFMODE = HIGH) and the Receiver outputs are clocked
relative to a recovered clock, it is necessary to frame the
Receiver before BIST is enabled.
Receive Elasticity Buffer
Each receive channel contains an Elasticity Buffer that is
designed to support multiple clocking modes. These buffers
allow data to be read using an Elasticity Buffer read-clock that
is asynchronous in both frequency and phase from the
Elasticity Buffer write clock, or to use a read clock that is
frequency coherent but with uncontrolled phase relative to the
Elasticity Buffer write clock.
Each Elasticity Buffer is 10-characters deep, and supports a
twelve-bit wide data path. It is capable of supporting a decoded
character, three status bits, and a parity bit for each character
present in the buffer. The write clock for these buffers is always
the recovered clock for the associated read channel.
The read clock for the Elasticity Buffers may come from one of
three selectable sources. It may be a
These Elasticity Buffers are also used to align the output data
streams when multiple channels are bonded together. More
details on how the Elasticity Buffer is used for Independent
Channel Modes and Channel Bonded Modes is discussed in
the next section. The Elasticity Buffers are bypassed
whenever the Decoders are bypassed (DECMODE = LOW).
When the Decoders and Elasticity Buffers are bypassed,
RXCKSELx must be set to MID.
Receive Modes
The operating mode of the receive path is set through the
RXMODE[1:0] inputs. The ‘Reserved for test’ settings
(RXMODE0 = M) is not allowed, even if the receiver is not
being used, as it will stop normal function of the device. When
the decoder is disabled, the RXMODE[1:0] settings are
ignored as long as they are not test modes. These modes
determine the type (if any) of channel bonding and status
reporting. The different receive modes are listed in Table 14.
Independent Channel Modes
In independent channel modes (RX Modes 0 and 2, where
RXMODE[1] = LOW), all four receive paths may be clocked in
any clock mode selected by RXCKSEL.
When RXCKSEL = LOW, all four receive channels are clocked
by REFCLK. RXCLKB± and RXCLKD± outputs are disabled
(High-Z), and the RXCLKA± and RXCLKC± outputs present a
buffered and delayed form of REFCLK. In this mode, the
Receive Elasticity Buffers are enabled. For REFCLK clocking,
the Elasticity Buffers must be able to insert K28.5 characters
and delete framing characters as appropriate.
The insertion of a K28.5 or deletion of a framing character can
occur at any time on any channel, however, the actual timing
on these insertions and deletions is controlled in part by the
• character-rate REFCLK (RXCKSEL = LOW and
• recovered clock from an alternate receive channel
DECMODE ≠ LOW)
(RXCKSEL = HIGH and DECMODE ≠ LOW).
how the transmitter sends its data. Insertion of a K28.5
character can only occur when the receiver has a framing
character in the Elasticity Buffer. Likewise, to delete a framing
character, one must also be present in the Elasticity Buffer. To
prevent a receive buffer overflow or underflow on a receive
channel, a minimum density of framing characters must be
present in the received data streams.
Table 14. Receive Operating Modes
When RXCKSEL = MID (or open), each received channel
Output Register is clocked by the recovered clock for that
channel. Since no characters may be added or deleted, the
receiver Elasticity Buffer is bypassed.
When RXCKSEL = HIGH in independent channel mode, all
channels are clocked by the selected recovered clock. This
selection is made using the RXCLKB+ and RXCLKD+ signals
as inputs per Table 15. This selected clock is always output on
RXCLKA± and RXCLKC±. In this mode the Receive Elasticity
Buffers are enabled. When data is output using a recovered
clock (RXCKSEL = HIGH), the receive channels are not
allowed to insert and delete characters, except as necessary
for Elasticity Buffer alignment.
When the Elasticity Buffer is used, prior to reception of valid
data, a Word Sync Sequence (or at least four framing
characters) must be received to center the Elasticity Buffers.
The Elasticity Buffer may also be centered by a device reset
operation initiated by TRSTZ input. However, following such
an event, the CYP(V)(W)15G0401DXB also requires a
framing event before it will correctly decode characters. When
RXCKSEL = HIGH, since the Elasticity Buffer is not allowed to
insert or delete framing characters, the transmit clocks on all
received channels must all be from a common source.
Table 15. Independent and Quad Channel Bonded
Recovered Clock or Master Channel Select
RX Mode
0
1
2
3
4
5
6
7
8
RXCLKB+
0
0
1
1
MM
MH
HM
LM
ML
HH
LH
HL
LL
Independent
Independent
Channel
Bonding
RXCLKD+
Quad
Quad
Dual
Dual
0
1
0
1
Operating Mode
CYW15G0401DXB
CYP15G0401DXB
CYV15G0401DXB
RXCLKA±/RXCLKC± Clock
Status A
Reserved for test
Status B
Status A
Reserved for test
Status B
Status A
Reserved for test
Status B
RXSTx Status Reporting
RXCLKA
RXCLKB
RXCLKC
RXCLKD
Source
Page 25 of 53