CYP15G0401DXB-BGC Cypress Semiconductor Corp, CYP15G0401DXB-BGC Datasheet - Page 19

• Manufacturer Part Number: CYP15G0401DXB-BGC
• Description: IC TXRX HOTLINK 256LBGA
• Manufacturer: Cypress Semiconductor Corp
• Series: HOTlink II™r
• Type: Transceiverr

Specifications of CYP15G0401DXB-BGC

• Package / Case: 256-LBGA Exposed Pad, 32-HLBGA
• Number Of Drivers/receivers: 4/4
• Protocol: Multiprotocol
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Product: PHY
• Supply Voltage (min): 3.135 V
• Supply Current: 1.06 A
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Channels: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CYP15G0401DX-EVAL - IC TXRX HOTLINK 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Document #: 38-02002 Rev. *L
When TXCKSEL = MID, all transmit channels operate
independently. In this mode, the SCSEL input is sampled only
by TXCLKA↑. When the character accepted in the Channel-A
Input Register has passed any selected validation and is ready
to be passed to the Encoder, the level captured on SCSEL is
passed to the Encoders of the remaining channels during this
same cycle.
Table 6. TX Modes 4 and 7 Encoding
Changing the state of SCSEL will change the relationship of
the characters to other channels. SCSEL should either be
used as a static configuration input, or changed only when the
state of TXCTx[1:0] on the alternate channels are such that
SCSEL is ignored during the change.
TX Mode 4 also supports an Word Sync Sequence. Unlike TX
Mode 3, this sequence starts when SCSEL and TXCTx[0] are
both high. With the exception of the combination of control bits
used to initiate the sequence, the generation and operation of
this Word Sync Sequence is the same as for TX Mode 3.
TX Mode 5—Atomic Word Sync generation without SCSEL.
When configured in TX Mode 5, the SCSEL signal is not used.
In addition to the standard character encodings, two additional
encoding mappings are controlled by the Channel Bonding
selection made through the RXMODE[1:0] inputs. For
non-bonded operation, the TXCTx[1:0] inputs for each
channel control the characters generated by that channel. The
specific characters generated by these bits are listed in
Table 7.
Table 7. TX Modes 5 and 8 Encoding, Non-bonded (RX-
MODE[1] = LOW)
TX Mode 5 also has the capability of generating an atomic
Word Sync Sequence. For the sequence to be started, the
TXCTx[1:0] inputs must both be sampled HIGH. The gener-
ation and operation of this Word Sync Sequence is the same
as TX Mode 3Two additional encoding maps are provided for
use when receive channel bonding is enabled. When
X
X
X
X
X
0
0
1
X
X
0
1
0
0
1
1
0
1
1
1
0
1
0
1
Encoded data character
K28.5 fill character
Special character code
16-character Word Sync Sequence
Encoded data character
K28.5 fill character
Special character code
16-character Word Sync Sequence
Characters Generated
Characters Generated
dual-channel bonding is enabled (RXMODE[1] = MID), the
CYP(V)(W)15G0401DXB is configured such that channels A
and B are bonded together to form a two-character-wide path,
and channels C and D are bonded together to form a second
two-character-wide path.
When operated in this two-channel bonded mode, the
TXCTA[0] and TXCTB[0] inputs control the interpretation of the
data on both the A and B channels, while the TXCTC[0] and
TXCTD[0] inputs control the interpretation of the data on both
the C and D channels. The characters on each half of these
bonded channels are controlled by the associated TXCTx[1]
bit. The specific characters generated by these control bit
combinations are listed in Table 8.
Note especially that any time TXCTB[0] is sampled HIGH, both
channels A and B start generating an atomic Word Sync
Sequence, regardless of the state of any of the other bits in the
A or B Input Registers. In a similar fashion, anytime TXCTD[0]
is sampled HIGH, both the C and D channels start generation
of an atomic Word Sync Sequence.
When RXMODE[1] = HIGH, the CYP(V)(W)15G0401DXB is
configured for quad-channel bonding, such that channels A, B,
C, and D are bonded together to form a four-character-wide
path. When operated in this mode, the TXCTA[0] and
TXCTB[0] inputs control the interpretation of the data on all
four channels. The characters generated on these bonded
channels are controlled by the associated TXCTx[1] bit. The
specific characters generated by these bits are listed in
Table 9.
Unlike dual-channel bonded modes, when all four channels
are bonded together, the TXCTC[0] and TXCTD[0] inputs are
ignored.
Transmit BIST
Each transmit channel contains an internal pattern generator
that can be used to validate both device and link operation.
These generators are enabled by the associated BOE[x]
signals listed in Table 10 (when the BISTLE latch enable input
is HIGH). When enabled, a register in the associated transmit
channel becomes a signature pattern generator by logically
converting to a Linear Feedback Shift Register (LFSR). This
LFSR generates a 511-character sequence that includes all
Data and Special Character codes, including the explicit
violation
pseudo-random sequence that can be matched to identical
LFSR in the attached Receiver(s). If the receive channels are
configured for common clock operation (RXCKSEL ≠ MID)
and Encoder is enabled (TXMODE[1] ≠ LOW) each pass is
preceded by a 16-character Word Sync Sequence to allow
Elasticity Buffer alignment and management of clock-
frequency variations.
When the BISTLE signal is HIGH, any BOE[x] input that is
LOW enables the BIST generator in the associated transmit
channel (or the BIST checker in the associated receive
channel). When BISTLE returns LOW, the values of all BOE[x]
signals are captured in the BIST Enable Latch. These values
remain in the BIST Enable Latch until BISTLE is returned
HIGH to open the latch. A device reset (TRSTZ sampled
LOW), presets the BIST Enable Latch to disable BIST on all
channels.
All data and data-control information present at the associated
TXDx[7:0] and TXCTx[1:0] inputs are ignored when BIST is
active on that channel.
symbols.
This
provides
CYW15G0401DXB
CYP15G0401DXB
CYV15G0401DXB
a
predictable
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yet