M69000 Asiliant Technologies, M69000 Datasheet - Page 141

• Manufacturer Part Number: M69000
• Manufacturer: Asiliant Technologies

Specifications of M69000

• Lead Free Status / Rohs Status: Supplier Unconfirmed

10-6
SR04
read/write at I/O address 3C5h with index at address 3C4h set to 04h
7-4
3
2
Note: Bit 3 of this register must be set to 0 for this bit to be effective. The selections made by this bit affect
Note:
1
0
&+,36
7
Reserved
Chain 4 Mode
0: The manner in which the frame buffer memory is mapped is determined by the setting of bit 2 of
this register.
1: The frame buffer memory is mapped in such a way that the function of address bits 0 and 1 are
altered so that they select planes 0 through 3.
The selections made by this bit affect both CPU read and write accesses to the frame buffer.
Odd/Even Mode
0: The frame buffer is mapped so that address bit 0 is used to select between sets of planes such
that even addresses select memory planes 0 and 2 and odd addresses select memory planes 1 and
3.
1: Addresses sequentially access data within a bit map, and the choice of which map is accessed
is made according to the value of the Plane Mask Register (SR02).
only CPU writes to the frame buffer.
This works in a way that is the inverse of (and is normally set to be the opposite of) bit 2 of the
Memory Mode Register (SR04).
Extended Memory Enable
0: Disable CPU accesses to more than the first 64KB of VGA standard memory.
1: Enable CPU accesses to the rest of the 256KB total VGA memory beyond the first 64KB.
This bit must be set to 1 to enable the selection and use of character maps in plane 2 via the
Character Map Select Register (SR03).
Reserved
69000 Databook
Memory Mode Register
6
Reserved
5
Subject to Change Without Notice
Sequencer Registers
4
Chain 4
3
Even
Odd/
2
Extended
Memory
Revision 1.3 8/31/98
1
Reserved
0