M69000 Asiliant Technologies, M69000 Datasheet - Page 181

• Manufacturer Part Number: M69000
• Manufacturer: Asiliant Technologies

Specifications of M69000

• Lead Free Status / Rohs Status: Supplier Unconfirmed

14-14
XR40
read/write at I/O address 3D7h with index at I/O address 3D6h set to 40h
7-2
1
0
XR41-XR4F
read/write at I/O address 3D7h with index at I/O address 3D6h set to 41h to 4Fh
7-0
&+,36
7
7
Reserved (Writable)
These bits should always be set to the value of 0.
Address Wrap
0: Only bits 0 through 17 of the memory address decode are used, causing the memory address
to wrap at 256K for all memory accesses either through the VGA porthole or linearly.
1: All memory address bits are used, allowing access to all of the graphics memory.
Memory Access Width
0: Selects the use of 16-bit accesses to memory to accommodate the standard VGA modes and
extended resolution modes with 4-bit color. This is the default after reset.
1: Selects the use of 64-bit accesses to memory to accommodate high resolution modes.
Memory Configuration Bits
The bits in each of these registers provide various ways to configure various aspects of the frame
buffer.
Each of these registers defaults to a particular setting, and some of these settings are non-zero.
These default settings should NEVER be changed.
69000 Databook
Memory Access Control Register
6
6
Memory Configuration Registers
Reserved (Writable)
5
5
(0000:00)
Subject to Change Without Notice
Memory Configuration Bits
Extension Registers
4
4
(xxxx:xxxx)
3
3
2
2
Address
Wrap
(0)
Revision 1.3 8/31/98
1
1
Memory
Access
(0)
0
0