M69000 Asiliant Technologies, M69000 Datasheet - Page 76

• Manufacturer Part Number: M69000
• Manufacturer: Asiliant Technologies

Specifications of M69000

• Lead Free Status / Rohs Status: Supplier Unconfirmed

7-4
5
4
3
2
1
Note: Accesses with only adjacent active byte enables are supported.
0
Note: Accesses with only adjacent active byte enables are supported.
&+,36
VGA Palette Snoop
0: Accesses to all VGA I/O locations including those for the palette will be claimed. All read and
write accesses to the palette will be performed normally. This is the default after reset.
1: Accesses to all VGA I/O locations, except for those for the palette, will be claimed. All reads will
be entirely ignored, but all writes will still update the palette. This permits accesses to the palette I/
O addresses to be answered by other devices that need to be able to snoop accesses to the palette.
Memory Write & Invalidate
This bit applies only to PCI Bus masters. Since this graphics controller never functions as a PCI
Bus master, this bit always returns a value of 0 when read.
Special Cycles
This graphics controller always ignores all special cycles, therefore this bit always returns the value
of 0 when read.
Bus Master
This graphics controller never functions as a PCI Bus master, therefore this bit always returns a
value of 0 when read.
Memory Access Enable
0: Disables access to the frame buffer memory locations within the range specified by the MBASE
Register. This is the default after reset.
1: Enables access to the frame buffer memory locations within the range specified by the MBASE
I/O Access Enable
0: Disables I/O port accesses. This is the default after reset.
1: Enables I/O port accesses.
69000 Databook
Register.
Subject to Change Without Notice
PCI Configuration Registers
Revision 1.3 8/31/98