M69000 Asiliant Technologies, M69000 Datasheet - Page 32

• Manufacturer Part Number: M69000
• Manufacturer: Asiliant Technologies

Specifications of M69000

• Lead Free Status / Rohs Status: Supplier Unconfirmed

2-8
Configuration Pins and ROM Interface
&+,36
BGA mBGA
L20
L19
C6
B16
A17
C15
A16
B15
C14
A15
B14
C13
A14
B13
D12
C12
A13
B12
D15
D18
C19
B20
C18
A20
B19
A19
B18
C17
D16
B10
C10
A9
B9
A8
C9
B8
A7
C8
B7
A6
C7
B6
A5
PIN
PIN
C12
D12
C11
A13
E12
F12
A12
B13
F11
A11
B12
D11
C10
D10
E11
A10
B11
E10
B10
R16
T16
69000 Databook
A7
B9
E8
A6
E8
A6
D7
C6
B6
D6
E9
B7
B7
E7
C9
D9
A4
A9
A8
E9
B9
A7
Pin Name
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
RMD0
RMD1
RMD2
RMD3
RMD4
RMD5
RMD6
RMD7
ROMOE#
(MCLKOUT)
RMA0
RMA1
RMA2
RMA3
RMA4
RMA5
RMA6
RMA7
RMA8
RMA9
RMA10
RMA11
RMA12
RMA13
RMA14
RMA15
RMA16
RMA17
Subject to Change Without Notice
Type
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
IN
IN
IN
IN
IN
IN
IN
IN
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
Active
Pin Descriptions
High
High
High
High
High
High
High
High
Low
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
Powered
IOVCC
& GND
IOVCC
& GND
IOVCC
& GND
IOVCC
& GND
Description
CFG0 through CFG15 are latched into
registers XR70 and XR71 on reset for use as
configuration inputs. Please see register
descriptions for XR70 and XR71 for complete
details on the configuration options.
RMD0 through RMD7 are used as BIOS ROM
data inputs during system startup (i.e., before
the system enables the graphics controller
memory interface).
BIOS ROM Output Enable.
May be configured as MCLK output in test
mode.
These pins are BIOS ROM address outputs
RMA0-17.
BIOS ROMs are not normally required in
portable computer designs (the graphics
system BIOS code is normally included in the
system BIOS ROM). However, the 69000
provides BIOS ROM interface capability for
development systems and add-in card flat
panel graphics controllers.
Since the PCI/AGP Bus specifications require
only one load on the bus for the entire
graphics subsystem, the BIOS ROM interface
is "through the chip".
Revision 1.3 8/31/98