M69000 Asiliant Technologies, M69000 Datasheet - Page 211

• Manufacturer Part Number: M69000
• Manufacturer: Asiliant Technologies

Specifications of M69000

• Lead Free Status / Rohs Status: Supplier Unconfirmed

14-44
XRCE
read/write at I/O address 3D7h with index at I/O address 3D6h set to CEh
Note: Before any value is written to bits other than bit 7 of register, bit 7 of this register should be set to 0
to select the default memory clock.
Note: All three of the registers used in specifying the loop parameters for the memory clock (XRCC -
XRCE) must be written, and in order from XRCC to XRCE, before the hardware will update the synthesizer’s
settings. This is a form of double-buffering that is intended to prevent fluctuations in the synthesizer’s output
as new values are being written to these registers.
7
6-4
&+,36
3-0
Clock Select
Memory
7
Memory Clock Select
0: The memory clock output is set to a preset frequency of40.00MHz. This is the default after reset.
1: The memory clock output is controlled by the loop parameters given to the memory clock
synthesizer using a group of three registers (XRCC-XRCE) which includes this one.
Post Divisor Select
These three bits select a value that specifies the post divisor, one of the loop parameters used in
controlling the frequency of the output of the synthesizer used to generate the memory clock. The
manner in which these bits are used to choose this value is shown in the table below:
Reserved
These bits always return the value of 0 when read.
69000 Databook
Memory Clock Divisor Select Register
A series of calculations are used to derive this value and the values for the other loop
parameters given a desired output frequency and a series of constraints placed on different
components within the synthesizer used to generate the memory clock. See the appendix
on clock generation for a detailed description of the process used to derive the loop
parameter values.
6
6 5 4
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Bits
Post Divisor Select
5
Subject to Change Without Notice
Post Divisor
Reserved
Reserved
Extension Registers
4
16
32
1
2
4
8
3
2
Reserved
Revision 1.3 8/31/98
1
0