M69000 Asiliant Technologies, M69000 Datasheet - Page 233

• Manufacturer Part Number: M69000
• Manufacturer: Asiliant Technologies

Specifications of M69000

• Lead Free Status / Rohs Status: Supplier Unconfirmed

15-18
FR13
read/write at I/O address 3D1h with index at I/O address 3D0h set to 13h
7-3
2
1-0
&+,36
7
Reserved (R/W) (reset state: 0000-0)
Increase Setup Time 16-bit Color STN-DD
0: Normal data setup time with respect to SHFCLK falling edge (default). Maximum SHFCLK
1: Extended data setup time with respect to SHFCLK falling edge. The setup time is increased by
This bit is effective only for 16-bit Color STN-DD when frame acceleration is enabled or for 8-bit
Color STN-DD when frame acceleration is disabled.
Color STN Pixel Packing
69000 Databook
frequency is DCLK/2 (1:1 duty cycle).
approximately half of a dot clock cycle. This is done by extending SHFCLK high time by half of
a dot clock cycle. Maximum SHFCLK frequency is DCLK/2.5 with a 1.5:1 duty cycle.
FP Format 3 Register
This determines the type of pixel packing (the RGB pixel output sequence) for color STN
panels. These bits must be programmed to 00 for monochrome STN panels and for all TFT
panels.
6
Bits
1 0
0 0
0 1
1 0
1 1
Reserved (R/W)
3-bit pack (default).
4-bit pack.
Reserved.
Extended 4-bit pack. Bits FR10 Bits 6-4 must be programmed
to 001. This setting may only be used for 8-bit interface color
STN SS panels.
5
Subject to Change Without Notice
Flat Panel Registers
Color STN Pixel Packing
4
3
Set Up Time
2
Revision 1.3 8/31/98
1
Pixel Packing
0