M69000 Asiliant Technologies, M69000 Datasheet - Page 206

• Manufacturer Part Number: M69000
• Manufacturer: Asiliant Technologies

Specifications of M69000

• Lead Free Status / Rohs Status: Supplier Unconfirmed

XRC4
read/write at I/O address 3D7h with index at I/O address 3D6h set to C4h
Note: All four of the registers used in specifying the loop parameters for dot clock 1 (XRC4 - XRC7) must
be written, and in order, from XRC4 to XRC7 before the hardware will update the synthesizer’s settings.
This is a form of double-buffering that is intended to prevent fluctuations in the synthesizer’s output as new
values are being written to these registers.
7-0
XRC5
read/write at I/O address 3D7h with index at I/O address 3D6h set to C5h
Note: All four of the registers used in specifying the loop parameters for dot clock 1 (XRC4 - XRC7) must
be written, and in order from XRC4 to XRC7, before the hardware will update the synthesizer’s settings.
This is a form of double-buffering that is intended to prevent fluctuations in the synthesizer’s output as new
values are being written to these registers.
7-0
&+,36
7
7
Dot Clock 1 VCO M-Divisor
This register the M-divisor, one of the loop parameters used in controlling the frequency of the
output of the synthesizer used to generate dot clock 1.
A series of calculations are used to derive this value and the values for the other loop parameters
given a desired output frequency and a series of constraints placed on different components within
the synthesizer used to generate dot clock 1. See appendix B for a detailed description of the
process used to derive the loop parameter values.
Dot Clock 1 VCO N-Divisor Bits 7-0
69000 Databook
Dot Clock 1 VCO M-Divisor Register
Dot Clock 1 VCO N-Divisor Register
This register provides the N-divisor, one of the loop parameters used in controlling the
frequency of the output of the synthesizer used to generate dot clock 1.
A series of calculations are used to derive this value and the values for the other loop
parameters given a desired output frequency and a series of constraints placed on different
components within the synthesizer used to generate dot clock 1. See appendix B for a
detailed description of the process used to derive the loop parameter values.
6
6
5
5
Subject to Change Without Notice
Dot Clock 1 VCO N-Divisor Bits 7-0
Dot Clock 1 VCO M-Divisor
Extension Registers
4
4
3
3
2
2
Revision 1.3 8/31/98
1
1
0
0
14-39