M69000 Asiliant Technologies, M69000 Datasheet - Page 92

• Manufacturer Part Number: M69000
• Manufacturer: Asiliant Technologies

Specifications of M69000

• Lead Free Status / Rohs Status: Supplier Unconfirmed

8-6
3-2
1
0
&+,36
Clock Select
These two bits select the dot clock.
RAM Access Enable
0: Disables CPU access to frame buffer.
1: Enables CPU access to frame buffer.
I/O Address Select
0: Sets the I/O address decode for ST01, FCR, and all CR registers to the 3Bx I/O address range
(for MDPA emulation).
1: Sets the I/O address decode for ST01, FCR, and all CR registers to the 3Dx I/O address range
(for CGA emulation).
69000 Databook
0 0
0 1
1 0
1 1
Bit
3 2
Selected Clock
CLK0 -- default 25MHz
(for standard VGA modes with a horizontal resolution of 320 or 640 pixels.
CLK1 -- default 28MHz
(for standard VGA modes with a horizontal resolution of 360 or 720 pixels.
CLK2
(normally for all extended modes or at any time a flat panel display is used)
(this selection was ‘reserved’ in the original VGA standard)
reserved
General Control and Status Registers
Subject to Change Without Notice
Revision 1.3 8/31/98