AD9991KCP Analog Devices Inc, AD9991KCP Datasheet
AD9991KCP
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AD9991KCP Summary of contents
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FEATURES 6-Phase Vertical Transfer Clock Support Correlated Double Sampler (CDS 10-Bit Variable Gain Amplifi er (VGA) 10-Bit 27 MHz A/D Converter Black Level Clamp with Variable Level Control Complete On-Chip Timing Generator Precision Timing Core ...
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AD9991 TABLE OF CONTENTS SPECIFICATIONS ............................................................... 3 Digital Specifi cations .......................................................... 3 Analog Specifi cations ........................................................... 4 Timing Specifi cations........................................................... 5 ABSOLUTE MAXIMUM RATINGS ..................................... 5 PACKAGE THERMAL CHARACTERISTICS ...................... 5 ORDERING GUIDE ............................................................. 5 PIN CONFIGURATION ....................................................... 6 PIN ...
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AD9991–SPECIFICATIONS Parameter TEMPERATURE RANGE Operating Storage POWER SUPPLY VOLTAGE AVDD (AFE Analog Supply) TCVDD (Timing Core Analog Supply) RGVDD (RG Driver) HVDD (H1–H4 Drivers) DRVDD (Data Output Drivers) DVDD (Digital) POWER DISSIPATION (See TPC 1 for Power Curves) 27 MHz, ...
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AD9991 ANALOG SPECIFICATIONS Parameter CDS* Allowable CCD Reset Transient Max Input Range before Saturation Max CCD Black Pixel Amplitude VARIABLE GAIN AMPLIFIER (VGA) Gain Control Resolution Gain Monotonicity Gain Range Min Gain (VGA Code 0) Max Gain (VGA Code 1023) ...
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... Unit JA board. +3.9 V +3.9 V +3.9 V +3.9 V Model +3.9 V AD9991KCP +3.9 V AD9991KCPRL –20°C to +85°C RGVDD + 0.3 V HVDD + 0.3 V DVDD + 0.3 V DVDD + 0.3 V DVDD + 0.3 V AVDD + 0.3 V 150 °C 350 °C –5– MHz, unless otherwise noted.) CLI Min Typ Max 37 14 ...
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AD9991 DRVDD DRVSS SUBCK 11 2 Pin Mnemonic Type Description Data Output Data Output Data Output Data Output Data Output Data Output ...
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TERMINOLOGY Differential Nonlinearity (DNL) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Thus every code must have a fi nite width. No missing codes guaranteed to 10-bit resolution ...
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AD9991–Typical Performance Characteristics 350 TOTAL H1-4 LOAD = 400 pF 300 V = 3.3V DD 250 200 150 100 10 15 SAMPLE RATE (MHz) TPC 1. Power Dissipation vs. Sample Rate 1.0 0.5 0 –0.5 –1.0 0 200 400 600 ...
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SYSTEM OVERVIEW Figure 1 shows the typical system block diagram for the AD9991 used in Master mode. The CCD output is processed by the AD9991’s AFE circuitry, which consists of a CDS, VGA, black level clamp, and A/D converter. The ...
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AD9991 PRECISION TIMING HIGH SPEED TIMING GENERATION The AD9991 generates high speed timing signals using the fl exible Precision Timing core. This core is the foundation for generating the timing used for both the CCD and the AFE: the reset ...
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Table II shows the correct register values for the corresponding edge locations. Figure 7 shows the default timing locations for all of the high speed clock signals. H-Driver and RG Outputs In addition to the programmable timing ...
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AD9991 P[0] POSITION PIXEL PERIOD RGr[0] RG Hr[0] H1/H3 H2/H4 CCD SIGNAL NOTES ALL SIGNAL EDGES ARE FULLY PROGRAMMABLE TO ANY OF THE 48 POSITIONS WITHIN ONE PIXEL PERIOD. DEFAULT POSITIONS FOR EACH SIGNAL ARE SHOWN. P[0] PIXEL PERIOD DCLK ...
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HORIZONTAL CLAMPING AND BLANKING The AD9991’s horizontal clamping and blanking pulses are fully programmable to suit a variety of applications. Individual control is provided for CLPOB, PBLK, and HBLK during the different regions of each fi eld. This allows the ...
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AD9991 Generating Special HBLK Patterns There are six toggle positions available for HBLK. Normally, only two of the toggle positions are used to generate the standard HBLK interval. However, the additional toggle positions may be used to generate special HBLK ...
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HORIZONTAL TIMING SEQUENCE EXAMPLE Figure 13 shows an example CCD layout. The horizontal register contains 28 dummy pixels, which will occur on each line clocked from the CCD. In the vertical direction, there are 10 optical black (OB) lines at ...
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AD9991 VERTICAL TIMING GENERATION The AD9991 provides a very fl exible solution for generating vertical CCD timing, and can support multiple CCDs and dif- ferent system architectures. The 6-phase vertical transfer clocks V1–V6 are used to shift each line of ...
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Vertical Pattern Groups (VPAT) The vertical pattern groups defi ne the individual pulse patterns for each V1–V6 output signal. Table V summarizes the registers available for generating each of the 10 V-pattern groups. The start polarity (VPOL) determines the starting ...
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AD9991 Vertical Sequences (VSEQ) The vertical sequences are created by selecting one of the 10 V-pattern groups and adding repeats, start position, and horizon- tal clamping, and blanking information V-sequences can be programmed, each using the registers ...
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Complete Field: Combining V-Sequences After the V-sequences have been created, they are combined to create different readout fi elds. A fi eld consists seven different regions, and within each region a different V-sequence can be selected. Figure ...
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AD9991 Generating Line Alternation for V-Sequence and HBLK During low resolution readout, some CCDs require a different number of vertical clocks on alternate lines. The AD9991 can support this by using the VPATREPO and VPATREPE regis- ters. This allows a ...
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Sweep Mode Operation The AD9991 contains an additional mode of vertical timing operation called Sweep mode. This mode is used to generate a large number of repetitive pulses that span multiple HD lines. One example of where this mode is ...
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AD9991 The example shown in Figure 22 illustrates this operation. The fi rst toggle position is 2, and the second toggle position non-Multiplier mode, this would cause the V-sequence to toggle at pixel 2 and then pixel ...
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MODE Register The MODE register is a single register that selects the fi eld tim- ing of the AD9991. Typically, all of the fi eld, V-sequence, and V-pattern group information is programmed into the AD9991 at startup. During operation, the ...
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AD9991 VERTICAL TIMING EXAMPLE To better understand how the AD9991 vertical timing generation is used, consider the example CCD timing chart in Figure 25. This particular example illustrates a CCD using a general 3-fi eld readout technique. As described in ...
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REV n– n–1 n– n–2 n– –25– AD9991 ...
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AD9991 SHUTTER TIMING CONTROL The CCD image exposure time is controlled by the substrate clock signal (SUBCK), which pulses the CCD substrate to clear out accumulated charge. The AD9991 supports three types of electronic shuttering: normal shutter, high precision shutter, ...
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If the exposure is generated using the TRIGGER register and the EXPOSURE register is set to zero, the behavior of the SUBCK will not be any different than the normal shutter or high precision shutter operations, in which the TRIGGER ...
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AD9991 It is possible to independently trigger the readout operation without triggering the exposure operation. This will cause the readout to occur at the next VD, and the SUBCK output will be suppressed according to the value of the READOUT ...
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STROBON_FD is the fi eld in which the STROBE is turned on, measured from the fi eld containing the last SUBCK before exposure begins. The STROBON_ LN PX register gives the line and pixel positions with respect to ...
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AD9991 –30– REV. 0 ...
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DC RESTORE 1.5V SHP SHD CCDIN CDS SHP SHD PRECISION TIMING GENERATION Figure 33. Analog Front End Functional Block Diagram ANALOG FRONT END DESCRIPTION AND OPERATION The AD9991 signal processing chain is shown in Figure 33. Each processing step is ...
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AD9991 Optical Black Clamp The optical black clamp loop is used to remove residual offsets in the signal chain and to track low frequency variations in the CCD’s black level. During the optical black (shielded) pixel inter- val on each ...
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VDD (INPUT) CLI (INPUT) t PWR SERIAL WRITES SYNC (INPUT) VD (OUTPUT) HD (OUTPUT) H2/H4 DIGITAL OUTPUTS H1/H3, RG, DCLK Figure 35. Recommended Power-Up Sequence and Synchronization, Master Mode POWER-UP AND SYNCHRONIZATION Recommended Power-Up Sequence for Master Mode When the ...
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AD9991 SYNC VD HD H124, RG, V1–V4, VSG, SUBCK NOTES 1. SYNC RISING EDGE RESETS VD/HD AND COUNTERS TO ZERO. 2. SYNC POLARITY IS PROGRAMMABLE USING SYNCPOL REGISTER (ADDR 0x13). 3. DURING SYNC LOW, ALL INTERNAL COUNTERS ARE RESET AND ...
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I/O Block Standby 3 (Default) AFE OFF Timing Core OFF CLO Oscillator OFF CLO VSG1 LO VSG2 LO VSG3 LO VSG4 LO VSG5 LO SUBCK LO VSUB ...
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AD9991 EXTERNAL SYNC FROM ASIC/DSP LINE/FIELD/DCLK TO ASIC/DSP DATA OUTPUTS DRVDD DRVSS 3V DRIVER VSUB 10 + SUPPLY SUBCK VSUB TO CCD CIRCUIT LAYOUT INFORMATION ...
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SERIAL INTERFACE TIMING All of the internal registers of the AD9991 are accessed through a 3-wire serial interface. Each register consists of an 8-bit address and a 24-bit data-word. Both the 8-bit address and 24-bit data- word are written starting ...
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AD9991 Register Address Banks 1 and 2 The AD9991 address space is divided into two different regis- ter banks, referred to as Register Bank 1 and Register Bank 2. Figure 41 illustrates how the two banks are divided. Register Bank ...
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Updating of New Register Values The AD9991’s internal registers are updated at different times, depending on the particular register. Table XV summarizes the four different types of register updates: 1. SCK Updated: Some of the registers in Bank 1 are ...
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AD9991 COMPLETE LISTING FOR REGISTER BANK 1 All registers are VD updated, except where noted: All address and default values are in hexadecimal. Data Bit Default Address Content Value Register Name 00 [11:0] 7 OPRMODE 01 [9:0] 0 VGAGAIN 02 ...
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Data Bit Default Address Content Value Register Name 30 [0] 0 CLIDIVIDE 31 [12:0] 01001 H1CONTROL 32 [12:0] 01001 H3CONTROL 33 [12:0] 00801 RGCONTROL 34 [1:0] 0 HBLKRETIME 35 [14:0] 1249 DRVCONTROL 36 [11:0] 00024 SAMPCONTROL 37 [8:0] 100 DOUTCONTROL ...
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AD9991 Data Bit Default Address Content Value Register Name 67 [1:0] 0 VSUBMODE 68 [12:0] 1000 VSUBON 69 [1:0] 1 MSHUTPOL 6A [23:0] 0 MSHUTON 6B [11:0] 0 MSHUTOFF_FD 6C [23:0] 0 MSHUTOFF_LNPX 6D [0] 1 STROBPOL 6E [11:0] 0 ...
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COMPLETE LISTING FOR REGISTER BANK 2 All V-pattern group and V-sequence registers are SCP updated, and all Field registers are VD updated. All address and default values are in hexadecimal. Table XXVI. V-Pattern Group 0 (VPAT0) Register Map Data Bit ...
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AD9991 Table XXVII. V-Pattern Group 1 (VPAT1) Register Map (continued) Data Bit Default Address Content Value Register Name 13 [11:0] 0 V5TOG1_1 [23:12] 0 V5TOG2_1 14 [11:0] 0 V5TOG3_1 [23:12] 0 V6TOG1_1 15 [11:0] 0 V6TOG2_1 [23:12] 0 V6TOG3_1 16 ...
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Table XXIX. V-Pattern Group 3 (VPAT3) Register Map (continued) Data Bit Default Address Content Value Register Name 26 [11:0] 0 V1TOG3_3 [23:12] 0 V2TOG1_3 27 [11:0] 0 V2TOG2_3 [23:12] 0 V2TOG3_3 28 [11:0] 0 V3TOG1_3 [23:12] 0 V3TOG2_3 29 [11:0] ...
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AD9991 Data Bit Default Address Content Value Register Name 3C [5:0] 0 VPOL_5 [11:6] 0 UNUSED [23:12] 0 VPATLEN_5 3D [11:0] 0 V1TOG1_5 [23:12] 0 V1TOG2_5 3E [11:0] 0 V1TOG3_5 [23:12] 0 V2TOG1_5 3F [11:0] 0 V2TOG2_5 [23:12] 0 V2TOG3_5 ...
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Table XXXII. V-Pattern Group 6 (VPAT6) Register Map (continued) Data Bit Default Address Content Value Register Name 50 [11:0] 0 V5TOG3_6 [23:12] 0 V6TOG1_6 51 [11:0] 0 V6TOG2_6 [23:12] 0 V6TOG3_6 52 [11:0] 0 FREEZE1_6 [23:12] 0 RESUME1_6 53 [11:0] ...
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AD9991 Table XXXIV. V-Pattern Group 8 (VPAT8) Register Map (continued) Data Bit Default Address Content Value Register Name 63 [11:0] 0 V2TOG1_8 [23:12] 0 V2TOG2_8 64 [11:0] 0 V3TOG3_8 [23:12] 0 V3TOG4_8 65 [11:0] 0 V3TOG1_8 [23:12] 0 V4TOG2_8 66 ...
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Table XXXV. V-Pattern Group 9 (VPAT9) Register Map (continued) Data Bit Default Address Content Value Register Name 79 [11:0] 0 V6TOG1_9 [23:12] 0 V6TOG2_9 7A [11:0] 0 V6TOG3_9 [23:12] 0 V6TOG4_9 7B [11:0] 0 V6TOG1_9 [23:12] 0 V6TOG2_9 7C [11:0] ...
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AD9991 Data Bit Default Address Content Value Register Name 88 [1:0] 0 HBLKMASK_1 [2] 0 CLPOBPOL_1 [3] 0 PBLKPOL_1 [7:4] 0 VPATSEL_1 [9:8] 0 VMASK_1 [11:10] 0 HBLKALT_1 [23:12] 0 UNUSED 89 [11:0] 0 VPATREPO_1 [23:12] 0 VPATREPE_1 8A [11:0] ...
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Data Bit Default Address Content Value Register Name 98 [1:0] 0 HBLKMASK_3 [2] 0 CLPOBPOL_3 [3] 0 PBLKPOL_3 [7:4] 0 VPATSEL_3 [9:8] 0 VMASK_3 [11:10] 0 HBLKALT_3 [23:12] 0 UNUSED 99 [11:0] 0 VPATREPO_3 [23:12] 0 VPATREPE_3 9A [11:0] 0 ...
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AD9991 Data Bit Default Address Content Value Register Name A8 [1:0] 0 HBLKMASK_5 [2] 0 CLPOBPOL_5 [3] 0 PBLKPOL_5 [7:4] 0 VPATSEL_5 [9:8] 0 VMASK_5 [11:10] 0 HBLKALT_5 [23:12] 0 UNUSED A9 [11:0] 0 VPATREPO_5 [23:12] 0 VPATREPE_5 AA [11:0] ...
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Data Bit Default Address Content Value Register Name B8 [1:0] 0 HBLKMASK_7 [2] 0 CLPOBPOL_7 [3] 0 PBLKPOL_7 [7:4] 0 VPATSEL_7 [9:8] 0 VMASK_7 [11:10] 0 HBLKALT_7 [23:12] 0 UNUSED B9 [11:0] 0 VPATREPO_7 [23:12] 0 VPATREPE_7 BA [11:0] 0 ...
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AD9991 Data Bit Default Address Content Value Register Name C8 [1:0] 0 HBLKMASK_9 [2] 0 CLPOBPOL_9 [3] 0 PBLKPOL_9 [7:4] 0 VPATSEL_9 [9:8] 0 VMASK_9 [11:10] 0 HBLKALT_9 [23:12] 0 UNUSED C9 [11:0] 0 VPATREPO_9 [23:12] 0 VPATREPE_9 CA [11:0] ...
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Data Bit Default Address Content Value Register Name D5 [3:0] 0 VPATSECOND_0 [9:4] 0 SGMASK_0 [21:10] 0 SGPATSEL_0 D6 [11:0] 0 SGLINE1_0 [23:12] 0 SGLINE2_0 D7 [11:0] 0 SCP5_0 [23:12] 0 SCP6_0 Data Bit Default Address Content Value Register Name ...
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AD9991 Data Bit Default Address Content Value Register Name E0 [3:0] 0 VSEQSEL_2 [4] 0 SWEEP0_2 [5] 0 MULTI0_2 [9:6] 0 VSEQSEL1_2 [10] 0 SWEEP1_2 [11] 0 MULTI1_2 [15:12] 0 VSEQSEL2_2 [16] 0 SWEEP2_2 [17] 0 MULTI2_2 [21:18] 0 VSEQSEL3_2 ...
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Data Bit Default Address Content Value Register Name E9 [3:0] 0 VSEQSEL4_3 [4] 0 SWEEP4_3 [5] 0 MULTI4_3 [9:6] 0 VSEQSEL5_3 [10] 0 SWEEP5_3 [11] 0 MULTI5_3 [15:12] 0 VSEQSEL6_3 [16] 0 SWEEP6_3 [17] 0 MULTI6_3 [23:18] UNUSED EA [11:0] ...
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AD9991 Data Bit Default Address Content Value Register Name F4 [11:0] 0 VDLEN_4 [23:12] 0 HDLAST_4 F5 [3:0] 0 VPATSECOND_4 [9:4] 0 SGMASK_4 [21:10] 0 SGPATSEL_4 F6 [11:0] 0 SGLINE1_4 [23:12] 0 SGLINE2_4 F7 [11:0] 0 SCP5_4 [23:12] 0 SCP6_4 ...
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PIN 1 INDICATOR 1.00 12 MAX 0.90 0.80 0.20 REF SEATING PLANE REV. 0 OUTLINE DIMENSIONS 56-Lead Lead Frame Chip Scale Package [LFCSP Body (CP-56) Dimensions shown in millimeters 8.00 0.60 MAX BSC SQ 0.60 ...
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–60– ...