AD9991KCP Analog Devices Inc, AD9991KCP Datasheet - Page 38

• Manufacturer Part Number: AD9991KCP
• Description: IC CCD SIGNAL PROCESSOR 56-LFCSP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 10-Bitr

Specifications of AD9991KCP

• Rohs Status: RoHS non-compliant
• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 56-LFCSP
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Input Voltage Range: 0.5V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 10b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 56
• Package Type: LFCSP EP
• Number Of Channels: 1
• Current - Supply: -
• Lead Free Status / RoHS Status: Not Compliant

Register Address Banks 1 and 2
The AD9991 address space is divided into two different regis-
ter banks, referred to as Register Bank 1 and Register Bank 2.
Figure 41 illustrates how the two banks are divided. Register
Bank 1 contains the registers for the AFE, miscellaneous func-
tions, VD/HD parameters, timing core, CLPOB masking, VSG
patterns, and shutter functions. Register Bank 2 contains all
of the information for the V-pattern groups, V-sequences, and
fi eld information.
AD9991
ADDR 0xFF
ADDR 0x8F
ADDR 0x00
ADDR 0x10
ADDR 0x20
ADDR 0x30
ADDR 0x40
ADDR 0x50
ADDR 0x60
ADDR 0x7F
MISCELLANEOUS REGISTERS
SWITCH TO REGISTER BANK 2
VSG PATTERN REGISTERS
INVALID—DO NOT ACCESS
CLPOB MASK REGISTERS
TIMING CORE REGISTERS
REGISTER BANK 1
SHUTTER REGISTERS
VD/HD REGISTERS
AFE REGISTERS
Figure 41. Layout of Internal Register Banks 1 and 2
WRITE TO ADDRESS 0x7F TO SWITCH REGISTER BANKS
–38–
When writing to the AD9991, address 0x7F is used to specify
which address bank is being written to. To write to Bank 1, the
LSB of address 0x7F should be set to 0; to write to Bank 2, the
LSB of address 0x7F should be set to 1.
Note that Register Bank 1 contains many unused addresses. Any
undefi ned addresses between address 0x00 and 0x7F are consid-
ered don’t cares, and it is acceptable if these addresses are fi lled
in with all 0s during a continuous register write operation. How-
ever, the undefi ned addresses above 0x7F must not be written to,
or the AD9991 may not operate properly.
ADDR 0x00
ADDR 0x7E
ADDR 0x7F
ADDR 0x80
ADDR 0xCF
ADDR 0xD0
ADDR 0xFF
SWITCH TO REGISTER BANK 1
FIELD 0–FIELD 5 REGISTERS
VSEQ0–VSEQ9 REGISTERS
VPAT0–VPAT9 REGISTERS
REGISTER BANK 2
REV. 0