AD9991KCP Analog Devices Inc, AD9991KCP Datasheet - Page 39

• Manufacturer Part Number: AD9991KCP
• Description: IC CCD SIGNAL PROCESSOR 56-LFCSP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 10-Bitr

Specifications of AD9991KCP

• Rohs Status: RoHS non-compliant
• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 56-LFCSP
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Input Voltage Range: 0.5V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 10b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 56
• Package Type: LFCSP EP
• Number Of Channels: 1
• Current - Supply: -
• Lead Free Status / RoHS Status: Not Compliant

Updating of New Register Values
The AD9991’s internal registers are updated at different times,
depending on the particular register. Table XV summarizes the
four different types of register updates:
Update Type
SCK Updated
VD Updated
SG Line Updated
SCP Updated
REV. 0
1. SCK Updated: Some of the registers in Bank 1 are updated
2. VD Updated: Most of the registers in Bank 1, as well as
The Bank Select register (addr 0x7F in Bank 1 and 2) is also
immediately, as soon as the 24th data bit (D23) is written.
These registers are used for functions that do not require
gating with the next VD boundry, such as power-up and reset
functions. These registers are lightly shaded in gray in the
Bank 1 register list.
SCK updated.
the Field registers in Bank 2, are updated at the next VD
falling edge. By updating these values at the next VD edge,
the current fi eld will not be corrupted and the new register
values will be applied to the next fi eld. The Bank 1 register
updates may be further delayed past the VD falling edge
by using the UPDATE register (addr 0x19). This will delay
the VD updated register updates to any HD line in the fi eld.
Note that the Bank 2 registers are not affected by the UPDATE
register.
SERIAL
WRITE
V1–V6
VSG
VD
HD
Register Bank
Bank 1 Only
Bank 1 and Bank 2
Bank 1 Only
Bank 2 Only
Figure 42. Register Update Locations (See Table XV for Defi nitions)
UPDATED
SCK
SCP 0
USE VSEQ2
UPDATED
REGION 0
VD
Table XV. Register Update Locations
Description
Register is immediately updated when the 24th data bit (D23) is clocked in.
Register is updated at the VD falling edge. VD updated registers in Bank 1 may be
delayed further by using the UPDATE register at address 0x19 in Bank 1. Bank 2
updates will not be affected by the UPDATE register.
Register is updated at the HD falling edge at the end of the SG-active line.
Register is updated at the next SCP when the register will be used.
SCP 1
UPDATED
SGLINE
USE VSEQ3
REGION 1
SG
–39–
SCP 2
USE VSEQ5
UPDATED
SCP
4. SCP Updated: In Bank 2, all of the V-pattern group and
3. SG-Line Updated: A few of the registers in Bank 1 are
updated at the end of the SG active line, at the HD falling
edge. These are the registers to control the SUBCK signal
so that the SUBCK output will not be updated until after
the SG line has been completed. These registers are darkly
shaded in gray in the Bank 1 register list.
V-sequence registers (addr 0x00 through 0xCF, exclud-
ing 0x7F) are updated at the next SCP, where they will
be used. For example, in Figure 42, this fi eld has selected
Region 1 to use V-Sequence 3 for the vertical outputs.
This means that a write to any of the V-Sequence 3 reg-
isters, or any of the V-pattern group registers that are
referenced by V-Sequence 3 will be updated at SCP1. If
multiple writes are done to the same register, the last one
done before SCP1 will be the one that is updated. Likewise,
register writes to any V-Sequence 5 registers will be updated
at SCP2, and register writes to any V-Sequence 8 registers
will be updated at SCP3.
REGION 2
SCP 3
USE VSEQ8
REGION 3
SCP 0
AD9991