AD9991KCP Analog Devices Inc, AD9991KCP Datasheet - Page 49

• Manufacturer Part Number: AD9991KCP
• Description: IC CCD SIGNAL PROCESSOR 56-LFCSP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 10-Bitr

Specifications of AD9991KCP

• Rohs Status: RoHS non-compliant
• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 56-LFCSP
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Input Voltage Range: 0.5V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 10b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 56
• Package Type: LFCSP EP
• Number Of Channels: 1
• Current - Supply: -
• Lead Free Status / RoHS Status: Not Compliant

Address Content Value
79
7A
7B
7C
7D
7E
Address Content Value
7F
Address Content Value
80
81
82
83
84
85
86
87
REV. 0
Data Bit Default
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
Data Bit Default
[0]
Data Bit Default
[1:0]
[2]
[3]
[7:4]
[9:8]
[11:10]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register Name
V6TOG1_9
V6TOG2_9
V6TOG3_9
V6TOG4_9
V6TOG1_9
V6TOG2_9
V6TOG3_9
V6TOG4_9
FREEZE1_9
RESUME1_9
FREEZE2_9
RESUME2_9
Register Name
BANKSELECT2
Register Name
HBLKMASK_0
CLPOBPOL_0
PBLKPOL_0
VPATSEL_0
VMASK_0
HBLKALT_0
UNUSED
VPATREPO_0
VPATREPE_0
VPATSTART_0
HDLEN_0
PBLKTOG1_0
PBLKTOG2_0
HBLKTOG1_0
HBLKTOG2_0
HBLKTOG3_0
HBLKTOG4_0
HBLKTOG5_0
HBLKTOG6_0
CLPOBTOG1_0
CLPOBTOG2_0
Table XXXV. V-Pattern Group 9 (VPAT9) Register Map (continued)
Table XXXVI. Register Map Selection (SCK Updated Register)
Table XXXVII. V-Sequence 0 (VSEQ0) Register Map
Description
V5 Toggle Position 1
V5 Toggle Position 2
V5 Toggle Position 3
V5 Toggle Position 4
V6 Toggle Position 1
V6 Toggle Position 2
V6 Toggle Position 3
V6 Toggle Position 4
V1–V6 Freeze Position 1
V1–V6 Resume Position 1
V1–V6 Freeze Position 2
V1–V6 Resume Position 2
Register Description
Register Bank Access from Bank 2 to Bank 1. 0 = Bank 1, 1 = Bank 2.
Description
Masking Polarity during HBLK. H1 [0]. H3 [1].
CLPOB Start Polarity
PBLK Start Polarity
Selected V-Pattern Group for V-Sequence 0
Enable Masking of V-Outputs (Specifi ed by Freeze/Resume Registers)
Enable HBLK Alternation
Unused
Number of Selected V-Pattern Group Repetitions for Odd Lines
Number of Selected V-Pattern Group Repetitions for Even Lines
Start Position in the Line for the Selected V-Pattern Group
HD Line Length (Number of Pixels) for V-Sequence 0
PBLK Toggle Position 1 for V-Sequence 0
PBLK Toggle Position 2 for V-Sequence 0
HBLK Toggle Position 1 for V-Sequence 0
HBLK Toggle Position 2 for V-Sequence 0
HBLK Toggle Position 3 for V-Sequence 0
HBLK Toggle Position 4 for V-Sequence 0
HBLK Toggle Position 5 for V-Sequence 0
HBLK Toggle Position 6 for V-Sequence 0
CLPOB Toggle Position 1 for V-Sequence 0
CLPOB Toggle Position 2 for V-Sequence 0
–49–
AD9991