FIN212ACMLX Fairchild Semiconductor, FIN212ACMLX Datasheet - Page 10

• Manufacturer Part Number: FIN212ACMLX
• Description: IC SERIAL/DESERIAL 12BIT 32MLP
• Manufacturer: Fairchild Semiconductor
• Series: SerDes™r
• Type: Serializer Deserializer with Multiple Frequency Ranger

Specifications of FIN212ACMLX

• Function: Serializer/Deserializer
• Data Rate: 560Mbps
• Input Type: LVCMOS
• Output Type: LVCMOS
• Number Of Inputs: 12
• Number Of Outputs: 12
• Voltage - Supply: 1.65 V ~ 3.6 V
• Operating Temperature: -30°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-MLP
• No. Of Inputs: 12
• No. Of Outputs: 12
• Supply Voltage Range: 2.5V To 3.6V, 1.65V To 3.6V
• Driver Case Style: MLP
• No. Of Pins: 32
• Termination Type: Solder
• Operating Temperature Range: -30°C To +70°C
• Rohs Compliant: Yes
• Operating Supply Voltage: 3.3 V
• Maximum Power Dissipation: 2.5 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: - 30 C
• Mounting Style: SMD/SMT
• Filter Terminals: Solder
• Digital Ic Case Style: MLP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: FIN212ACMLXTR

AC Electrical Characteristics
Values are provided for over-supply voltage and operating temperature ranges, unless otherwise specified.
© 2008 Fairchild Semiconductor Corporation
FIN212AC • Rev. 1.1.0
Symbol
Serializer Input Operating Conditions
Serializer AC Electrical Characteristics
Phase Lock Loop (PLL) AC Electrical Characteristics
Deserializer AC Electrical Characteristics
Symbol
t
RCOL
t
t
t
t
t
PDV
f
t
t
SPWH/L
t
TPLLS0
TPLLD0
TPLLD1
CKREF
f
t
CPWH
CPWL
t
t
TCCD
STRB
CLKT
STC
HTC
Parameter
Setup: DIRI= 0, CKSI and DS are valid signals.
Data Valid
Parameter
CKREF Clock Frequency
(5MHz - >40MHz);
Strobe Frequency Relative to
CKREF Frequency
CKREF DC
CKREF DC
LVCMOS Input Transition Time
STROBE Pulse Width HIGH/LOW
DP
(DIRI=1, f=5MHz)
DP
(DIRI=1, f=5MHz)
Transmitter Clock Input to Clock
Output Delay
Serializer PLL Stabilization Time
PLL Disable Time Loss of Clock
PLL Power-Down Time
DP[1:12]
CKP
(n)
(n)
CKP
Setup to STROBE
Hold to STROBE
50%
(6)
t
75%
RCOH
t
RCOP
Data
t
RCOL
25%
50%
t
PDV
(5)
Test Conditions
f
f
T=1/f
T=1/f
10-90%
T=1/f
CKS+
DIRI=1, f
CKREF toggling and stable
STROBE
CKS-
CKREF
CKREF
Setup Time
Hold Time
S T R O B E
D P [1 : 1 2]
CKP
S T R O B E
D P [1 : 1 2]
CKREF
CKREF
CKREF
=f
≠ f
Test Conditions
f
f
f
f
Data Valid to CKP HIGH (Rising Edge
STROBE), C
STRB
STRB
STRB
STRB
STRB
CKREF
STRB
Note: STROBE=CKREF
=f
=f
=.5x f
=.5x f
CKREF
CKREF
=f
10
STRB
VDD/2
CKREF
CKREF
t
V
L
TCCD
DIFF
=5pF
t
S T C
=0
D a ta
S1=0, S0=1
S1=1, S0=0
S1=1, S0=1
PLL1=0, PLL0=0
PLL1=0, PLL0=1
PLL1=1, PLL0=0
PLL1=1, PLL0=1
PWS1
0
0
1
1
D ata
VDD/2
t
PWS0
0
1
0
1
RCCD
t
H T C
Min.
21a+1.5
T x
200
0.2
0.2
2.5
2.0
18
10
13a-3
17a-3
5
Min.
7a-3
7a-3
8a-3
4
/
14
Typ.
0.5
0.5
Typ.
Max.
www.fairchildsemi.com
T x
23a+6.5
33
30.0
20.0
100
100
600
0.8
0.8
40
14
28
50
20
13a+3
17a+3
10
1
Max.
7a+3
7a+3
8a+3
/
3
/
14
Unit
f
MHz
% of
CKREF
ns
ns
ns
ns
ns
μs
μs
ns
Unit
T
T
ns
ns