FIN212ACMLX Fairchild Semiconductor, FIN212ACMLX Datasheet - Page 7

• Manufacturer Part Number: FIN212ACMLX
• Description: IC SERIAL/DESERIAL 12BIT 32MLP
• Manufacturer: Fairchild Semiconductor
• Series: SerDes™r
• Type: Serializer Deserializer with Multiple Frequency Ranger

Specifications of FIN212ACMLX

• Function: Serializer/Deserializer
• Data Rate: 560Mbps
• Input Type: LVCMOS
• Output Type: LVCMOS
• Number Of Inputs: 12
• Number Of Outputs: 12
• Voltage - Supply: 1.65 V ~ 3.6 V
• Operating Temperature: -30°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-MLP
• No. Of Inputs: 12
• No. Of Outputs: 12
• Supply Voltage Range: 2.5V To 3.6V, 1.65V To 3.6V
• Driver Case Style: MLP
• No. Of Pins: 32
• Termination Type: Solder
• Operating Temperature Range: -30°C To +70°C
• Rohs Compliant: Yes
• Operating Supply Voltage: 3.3 V
• Maximum Power Dissipation: 2.5 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: - 30 C
• Mounting Style: SMD/SMT
• Filter Terminals: Solder
• Digital Ic Case Style: MLP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: FIN212ACMLXTR

Application Diagrams
© 2008 Fairchild Semiconductor Corporation
FIN212AC • Rev. 1.1.0
MASTER CLK
Baseband
Processor
PIXEL CLK
YUV[7:0]
Baseband
Processor
HSYNC
VSYNC
/RES
SYS CLK
Data[7:0]
Figure 7. 8-Bit WRITE-Only Microcontroller Interface (Example Shows BGA 42-Pin Package)
/RES
Serializer Configuration:
20MHz to 40MHz Frequency Range (S1=0, S0=1)
Normal Mode (PLL1=0; PLL0=1)
Master clock bypass mode.
Serializer Configuration:
20MHz to 40MHz Frequency Range (S1=0, S0=1)
CKREF is twice as fast STROBE (PLL1=1; PLL0=0)
CKREF=26MHz & STROBE Frequency=10 MHz
/CS0
/CS1
/WE
A0
NC
B3:E1
E2
F1
G1:F2
VDDP1
A6
B5
C1
Figure 6. 8-Bit YUV 1.3MPixel CMOS Imager In Clock Pass-Through Mode
F6
G3
G4
A3
G5
G6
NC
B3:E1
E2
F1
F2
G1
A6
B5
C1
CKREF
STROBE
CKP
DP[8:1]
DP[9]
DP[10]
DP[12:11]
DIRI
PWS1
PWS0
XTRM
S1
S0
D3
F6
G3
G4
A4
G5
G6
VDDP1
VDDP
CKREF
STROBE
CKP
DP[8:1]
DP[9]
DP[10]
DP[11]
DP[12]
DIRI
PLL1
PLL0
CTL_ADJ
S1
S0
(Continued)
Deserializer
D3
FIN212AC
VDDP1
VDDP
GND
FIN212AC
Serializer
E4
VDDS/A
GND
CKSO+
CKSO-
CKSI+
/DIRO
CKSI-
DSI+
DSI-
VDDS/A
E4
CKSO+
F4
CKSO-
CKSI+
DSO+
/DIRO
CKSI-
DSO-
C5
C6
D5
D6
E6
E5
B6
NC
F4
VDD
C5
C6
D6
D5
E6
E5
B6
NC
NC
NC
NC
E5
E6
D6
D5
VDD
C6
C5
B6
NC
NC
NC
CKSI+
CKSI-
DSO+
DSO-
CKSO-
CKSO+
/DIRO
E5
E6
D5
D6
C6
C5
B6
E4
VDDS/A
7
FIN212AC
Serializer
Deserializer Configuration:
~2 – 3ns output edge rates (S1=0, S0=1)
~50% CKP PW,(PWS1=PWS0=0)
CKSI+
CKSI-
DSI+
DSI-
CKSO-
CKSO+
/DIRO
Deserializer Configuration:
~7 – 8ns output edge rates (S1=1, S0=0)
~50% CKP PW,(PWS1=PWS0=0)
E4
GND
VDDS/A
F4
Deserializer
FIN212AC
DP[12:11]
CTL_ADJ
STROBE
VDDP
CKREF
DP[8:1]
GND
VDDP2
DP[10]
F4
DP[9]
D3
PLL1
PLL0
CKP
DIRI
S1
S0
STROBE
VDDP
CKREF
DP[8:1]
VDDP2
DP[10]
DP[11]
DP[12]
PWS1
PWS0
XTRM
DP[9]
F6
G3
G4
A4
G5
G6
D3
CKP
DIRI
C1
A6
B5
B3:E1
E2
F1
G1:F2
S1
S0
VDDP2
E2
F1
F2
G1
A3
F6
G3
G4
G5
G6
B3:E1
C1
A6
B5
NC
MASTER CLK
PIXEL CLK
YUV[7:0]
HSYNC
VSYNC
/RES
MAIN LCD
/WE
DATA[7:0]
A0
/CS
/RES
/WE
DATA[7:0]
A0
/CS
/RES
SUB LCD
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