N25Q128A11B1240F Numonyx - A DIVISION OF MICRON SEMICONDUCTOR PRODUCTS, INC., N25Q128A11B1240F Datasheet - Page 116

• Manufacturer Part Number: N25Q128A11B1240F
• Description: IC SRL FLASH 128MB NMX 24-BGA
• Manufacturer: Numonyx - A DIVISION OF MICRON SEMICONDUCTOR PRODUCTS, INC.
• Series: Forté™r

Specifications of N25Q128A11B1240F

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 128M (16M x 8)
• Speed: 108MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 1.7 V ~ 2 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 24-TBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: N25Q128A11B1240F

9.2.2
9.2.3
Note:
116/185
DQ0
DQ1
C
S
0
Instruction
1
2
Dual Command Fast Read (DCFR)
The Dual Command Fast Read (DCFR) instruction allows to read the memory in DIO-SPI
protocol, parallelizing the instruction code, the address and the output data on two pins
(DQ0 and DQ1). The Dual Command Fast Read (DCFR) instruction can be issued, when
the device is set in DIO-SPI mode, by sending to the memory indifferently one of the 3
instructions codes: 0Bh, 3Bh or BBh, the effect is exactly the same. The 3 instruction codes
are all accepted to help the application code porting from Extended SPI protocol to DIO-SPI
protocol.
Apart for the parallelizing on two pins of the instruction code, the Dual Command Fast Read
instruction functionality is exactly the same as the Dual I/O Fast Read of the Extended SPI
protocol, please refer to
Figure 45. Dual Command Fast Read instruction and data-out sequence DIO-SPI
Read OTP (ROTP)
The Read OTP (ROTP) instruction is used to read the 64 bytes OTP area in the DIO-SPI
protocol. The instruction functionality is exactly the same as the Read OTP instruction of the
Extended SPI protocol; the only difference is that in the DIO-SPI protocol instruction code,
address and output data are all parallelized on the two pins DQ0 and DQ1.
The dummy bits can not be parallelized since these clock cycles are requested to perform
the internal reading operation.
3
23 21 19 17
22 20 18 16
4
5
6
7
24-Bit Address
15 13 11 9
14 12 10 8
8
9 10 11
Section 9.1.5: Dual I/O Fast Read
12 13 14 15
7
6
5
4
3
2
1
0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
Dummy cycles
for further details.
7
MSB
6
Data Out 1
5
4
Dual_Command_Fast_Read
3
2
1
0
MSB
6
7
Data Out n
4
5
2
3
0
1