N25Q128A11B1240F Numonyx - A DIVISION OF MICRON SEMICONDUCTOR PRODUCTS, INC., N25Q128A11B1240F Datasheet - Page 28
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N25Q128A11B1240F
Manufacturer Part Number
N25Q128A11B1240F
Description
IC SRL FLASH 128MB NMX 24-BGA
Manufacturer
Numonyx - A DIVISION OF MICRON SEMICONDUCTOR PRODUCTS, INC.
Series
Forté™r
Datasheet
1.N25Q128A11B1241F.pdf
(185 pages)
Specifications of N25Q128A11B1240F
Format - Memory
FLASH
Memory Type
FLASH
Memory Size
128M (16M x 8)
Speed
108MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
1.7 V ~ 2 V
Operating Temperature
-40°C ~ 85°C
Package / Case
24-TBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
N25Q128A11B1240F
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
N25Q128A11B1240F
Manufacturer:
Micron Technology Inc
Quantity:
10 000
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5.2.4
5.2.5
5.2.6
5.2.7
5.2.8
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The DIO-SPI protocol is similar to the Extended SPI protocol i.e., to program one data byte
two instructions are required:
This is followed by the internal Program cycle (of duration tPP).
To spread this overhead, the Dual Command Page Program (DCPP) instruction allows up to
256 bytes to be programmed at a time (changing bits from 1 to 0), provided that they are
consecutive addresses on the same page of memory.
For optimized timings, it is recommended to use the DCPP instruction to program all
consecutive targeted bytes in a single sequence versus using several DCPP sequences
with each containing only a few bytes. See
Subsector Erase, Sector Erase and Bulk Erase
Similar to the Extended SPI protocol, in the DIO-SPI protocol to erase the memory bytes to
all 1s (FFh) the Subsector Erase (SSE), the Sector Erase (SE) and the Bulk Erase (BE)
instructions are available. These instructions start an internal Erase cycle (of duration tSSE,
tSE or tBE).
The Erase instruction must be preceded by a Write Enable (WREN) instruction.
Subsector Erase is only available on the 8 Bottom (Top) boot sectors, and is not available in
uniform architecture parts
Polling during a Write, Program or Erase cycle
Similar to the Extended SPI protocol, in the DIO-SPI protocol it is possible to monitor if the
internal write, program or erase operation is completed, by polling the dedicated register bits
by using the Read Status Register (RDSR) or Read Flag Status Register (RFSR)
instructions, the only obvious difference is that instruction codes, addresses and output data
are transmitted across two data lines.
Read and Modify registers
Similar to the Extended SPI protocol, the only obvious difference is that instruction codes,
addresses and output data are transmitted across two data lines
Active Power and Standby Power modes
Similar to the Extended SPI protocol, when Chip Select (S) is Low, the device is selected,
and in the Active Power mode. When Chip Select (S) is High, the device is deselected, but
could remain in the Active Power mode until all internal cycles have completed (Program,
Erase, Write Cycles). The device then goes in to the Standby Power mode. The device
consumption drops to ICC1.
HOLD (or Reset) condition
The HOLD (or Reset i.e. for parts having the reset functionality instead of hold pin) signal
has exactly the same behavior in DIO-SPI protocol as do in Extended SPI protocol, so
please refer to section 5.1.10, Hold (or Reset) condition” in the Extend SPI protocol section
for further details.
Write Enable (WREN), which is one byte, and a
Dual Command Page Program (DCPP) sequence, which consists of four bytes plus
data.
Table 33.: AC
Characteristics.
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