N25Q128A11B1240F Numonyx - A DIVISION OF MICRON SEMICONDUCTOR PRODUCTS, INC., N25Q128A11B1240F Datasheet - Page 97

• Manufacturer Part Number: N25Q128A11B1240F
• Description: IC SRL FLASH 128MB NMX 24-BGA
• Manufacturer: Numonyx - A DIVISION OF MICRON SEMICONDUCTOR PRODUCTS, INC.
• Series: Forté™r

Specifications of N25Q128A11B1240F

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 128M (16M x 8)
• Speed: 108MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 1.7 V ~ 2 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 24-TBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: N25Q128A11B1240F

9.1.17
Byte
0
Byte
1
Byte
Figure 26. How to permanently lock the OTP bytes
Subsector Erase (SSE)
For devices with bottom or top architecture, at the bottom (or top) of the addressable area
there are 8 boot sectors, each one having 16 4Kbytes subsectors. The Subsector Erase
(SSE) instruction sets to '1' (FFh) all bits inside the chosen subsector. Before it can be
accepted, a Write Enable (WREN) instruction must previously have been executed. After
the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable
Latch (WEL).
The Subsector Erase (SSE) instruction is entered by driving Chip Select (S) Low, followed
by the instruction code, and three address bytes on Serial Data input (DQ0). Any address
inside the subsector is a valid address for the Subsector Erase (SSE) instruction. Chip
Select (S) must be driven Low for the entire duration of the sequence.
Chip Select (S) must be driven High after the eighth bit of the last address byte has been
latched in, otherwise the Subsector Erase (SSE) instruction is not executed. As soon as
Chip Select (S) is driven High, the self-timed Subsector Erase cycle (whose duration is
tSSE) is initiated. While the Subsector Erase cycle is in progress, the Status Register may
be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP)
bit is 1 during the self-timed Subsector Erase cycle, and is 0 when it is completed. At some
unspecified time before the cycle is complete, the Write Enable Latch (WEL) bit is reset.
A Subsector Erase (SSE) instruction issued to a sector that is hardware or software
protected, is not executed.
Any Subsector Erase (SSE) instruction, while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on the cycle that is in progress.
Any Subsector Erase (SSE) instruction in devices with uniform architecture (meaning no
boot sectors with subsectors) is rejected without having any effects on the device.
2
64 data bytes
Bit 1 to bit 7 are not programmable
X
X
X
X
X
X
X
bit 0
OTP control byte
When bit 0 = 0
the 64 OTP bytes
become read only
Byte
63
ai13587
Byte
64
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