N25Q128A11B1240F Numonyx - A DIVISION OF MICRON SEMICONDUCTOR PRODUCTS, INC., N25Q128A11B1240F Datasheet - Page 94

• Manufacturer Part Number: N25Q128A11B1240F
• Description: IC SRL FLASH 128MB NMX 24-BGA
• Manufacturer: Numonyx - A DIVISION OF MICRON SEMICONDUCTOR PRODUCTS, INC.
• Series: Forté™r

Specifications of N25Q128A11B1240F

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 128M (16M x 8)
• Speed: 108MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 1.7 V ~ 2 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 24-TBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: N25Q128A11B1240F

9.1.15
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DQ0
DQ1
DQ2
DQ3
C
S
If more than 256 bytes are sent to the device, previously latched data are discarded and the
last 256 data bytes are guaranteed to be programmed correctly within the same page. If less
than 256 data bytes are sent to device, they are correctly programmed at the requested
addresses without having any effects on the other bytes in the same page.
For optimized timings, it is recommended to use the Quad Input Fast Program (QIFP)
instruction to program all consecutive targeted bytes in a single sequence rather to using
several Quad Input Fast Program (QIFP) sequences each containing only a few bytes See
Table 33.: AC
Chip Select (S) must be driven High after the eighth bit of the last data byte has been
latched in, otherwise the Quad Input Fast Program (QIFP) instruction is not executed.
As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose
duration is tPP) is initiated. While the Quad Input Fast Program (QIFP) cycle is in progress,
the Status Register may be read to check the value of the Write In Progress (WIP) bit. The
Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle, and 0 when it is
completed. At some unspecified time before the cycle is completed, the Write Enable Latch
(WEL) bit is reset.
A Quad Input Fast Program (QIFP) instruction applied to a page that is protected by the
Block Protect (BP3, BP2, BP1, BP0 and TB) bits is not executed.
A Quad Input Fast Program cycle can be paused by mean of Program/Erase Suspend
(PES) instruction and resumed by mean of Program/Erase Resume (PER) instruction.
Figure 23. Quad Input Fast Program instruction sequence
Quad Input Extended Fast Program
The Quad Input Extended Fast Program (QIEFP) instruction is very similar to the Quad
Input Extended Fast Program (QIFP), except that the address bits are shifted in on four pins
(pin DQ0, pin DQ1, pin W/VPP/DQ2 and pin HOLD/DQ3) instead of only one.
0
‘1’
1
Instruction
2
3
Characteristics.
4
5
6
7
23 22 21
8
9 10
24-bit address
Don’t Care
Don’t Care
Don’t Care
3
28 29 30 31 32 33
2
1
0
4
7
MSB
5
6
1
Data In
0
3
1
2
34 35 36
4
7
MSB
5
6
2
0
1
3
2
7
MSB
4
5
6
3
Data In
37
0
3
1
2
MSB
38
4
7
5
6
4
39
3
0
1
2
40
4
5
7
6
MSB
Quad_Input_Fast_Program
5
Data In
41
0
1
3
2
42
4
5
7
6
MSB
6
43
1
2
3
0