N25Q128A11B1240F Numonyx - A DIVISION OF MICRON SEMICONDUCTOR PRODUCTS, INC., N25Q128A11B1240F Datasheet - Page 31
N25Q128A11B1240F
Manufacturer Part Number
N25Q128A11B1240F
Description
IC SRL FLASH 128MB NMX 24-BGA
Manufacturer
Numonyx - A DIVISION OF MICRON SEMICONDUCTOR PRODUCTS, INC.
Series
Forté™r
Datasheet
1.N25Q128A11B1241F.pdf
(185 pages)
Specifications of N25Q128A11B1240F
Format - Memory
FLASH
Memory Type
FLASH
Memory Size
128M (16M x 8)
Speed
108MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
1.7 V ~ 2 V
Operating Temperature
-40°C ~ 85°C
Package / Case
24-TBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
N25Q128A11B1240F
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
N25Q128A11B1240F
Manufacturer:
Micron Technology Inc
Quantity:
10 000
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5.3.6
5.3.7
5.3.8
5.3.9
Read and Modify registers
The read and modify register instructions are available and behave in QIO-SPI protocol
exactly as they do in Extended SPI protocol, the only difference is that instruction codes,
addresses and output data are transmitted across 4 data lines.
Active Power and Standby Power modes
Exactly as in Extended SPI protocol, when Chip Select (S) is Low, the device is selected,
and in the Active Power mode. When Chip Select (S) is High, the device is deselected, but
could remain in the Active Power mode until all internal (Program, Erase, Write) Cycles
have completed. The device then goes in to the Standby Power mode. The device
consumption drops to ICC1.
HOLD (or Reset) condition
The HOLD (Hold) feature (or Reset feature, for parts having the reset functionality instead of
hold) is disabled in QIO-SPI protocol when the device is selected: the Hold (or Reset)/ DQ3
pin always behaves as an I/O pin (DQ3 function) when the device is deselected. For parts
with reset functionality, it is still possible to reset the memory when it is deselected (C signal
high).
VPP pin Enhanced Supply Voltage feature
It is possible in the QIO-SPI protocol to use the VPP pin as an enhanced supply voltage, but
the intention to use VPP as accelerated supply voltage must be declared by setting bit 3 of
the VECR to 0.
In this case, to accelerate the Program cycle the VPP pin must be raised to VPPH after the
device has received the last data to be programmed within 200ms. If the VPP is not raised
within 200ms, the program operation starts with the standard internal cycle speed as if the
Vpp high voltage were not used, and a flag error appears on Flag Status Register bit 3".
31/185
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