KIT_TC1797_SK Infineon Technologies, KIT_TC1797_SK Datasheet - Page 17

• Manufacturer Part Number: KIT_TC1797_SK
• Description: KIT STARTER AUDO FUTURE TC1797
• Manufacturer: Infineon Technologies
• Series: Audo Futurer
• Type: MCUr

Specifications of KIT_TC1797_SK

• Contents: Board, Adapters, Cables, CD, Power Supply
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: TC1797
• Other names: KITTC1797SKIN

Example
In this example, the word load from address 0xD000000E is split into 2 half-
word accesses, since it spans a 128-bit boundary in LDRAM. The double-word
store encounters the circular buffer wrap condition and should be split into 2
word accesses, to the top and bottom of the circular buffer. However, due to the
bug, the first access takes the transfer data size from the second part of the un-
aligned load and only 16-bits of data are written. Note that the presence of an
optional IP instruction between the load and store transactions does not prevent
the problem, since the load and store transactions are back-to-back in the LS
pipeline.
Case 2
Case 2 is similar to case 1, and occurs where a load instruction using circular
addressing mode encounters the circular buffer wrap-around condition, and is
preceded in the LS pipeline by a multi-access load instruction. However, for
case 2 to be a problem it is necessary that the first access of the load instruction
encountering the circular buffer wrap-around condition (the access to the top of
the circular buffer) also encounters a conflict condition with the contents of the
CPU store buffer. Again, in this case the first access of the load instruction using
circular addressing mode may incorrectly use the transfer data size from the
second part of the multi-access load instruction. Since half-word load
instructions must be half-word aligned, and ld.a instructions must be word
aligned, they cannot trigger the circular buffer wrap-around condition. As such,
this case only affects the following instructions using circular addressing mode:
ld.w, ld.d, ld.da.
TC1797, EES-AC, ES-AC, AC
...
LDA
LDA
LDA
...
ld.w d6, [a8]
add
st.d [a12/a13+c], d0/d1 ; Circular Buffer wrap, 32+32
...
a8,
a12, 0xD0000820 ; Circular Buffer Base
a13, 0x00180014 ; Circular Buffer Limit and Index
d4, d3, d2
0xD000000E ; Address of un-aligned load
; Un-aligned load, split 16+16
; Optional IP instruction
17/101
Functional Deviations
Rel. 1.3, 18.12.2009
Errata Sheet