KIT_TC1797_SK Infineon Technologies, KIT_TC1797_SK Datasheet - Page 86

• Manufacturer Part Number: KIT_TC1797_SK
• Description: KIT STARTER AUDO FUTURE TC1797
• Manufacturer: Infineon Technologies
• Series: Audo Futurer
• Type: MCUr

Specifications of KIT_TC1797_SK

• Contents: Board, Adapters, Cables, CD, Power Supply
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: TC1797
• Other names: KITTC1797SKIN

...
Method #2
For applications where the time prior to execution of the BISR instruction is
critical, the priority number of the interrupted task may be read from the CSA
pointed to by the PCXI after execution of the BISR instruction.
...
bisr
mfcr
sh.h
insert
mov.a
ld.bu
...
Note that contrary to the TriCore architecture specification, no DSYNC
instruction is stricly necessary after the BISR (or SVLCX) instruction, in either
the TriCore1.3 or TriCore1.3.1, to ensure the previous CSA contents are
flushed to memory. In both TriCore1.3 and TriCore1.3.1, any lower context save
operation (BISR or SVLCX) will automatically flush any cached upper context
to memory before the lower context is saved.
EBU_TC.H005 Potential live-lock situation on concurrent CPU and PCP
accesses to external memories
If a master (CPU, PCP, DMA) is already accessing an external memory, every
later access from another master will be retried on hardware level. Under very
improbable timing conditions, it may lead to a live-lock scenario, for example:
•
•
•
TC1797, EES-AC, ES-AC, AC
PCP polling continuously for a semaphore on an external memory.
CPU executing code from external memory in order to release the
semaphore.
The CPU may never get access to the EBU if the PCP access started
before.
d15, [a15]0x3
#<New Priority Number>
d15, #0xFE00
d14, d15, #12
d15, d14, d15, #6, #16 ; Merge PCX offset to d15
a15, d15
86/101
; Load byte containing PCPN
; Copy PCXI to d15
; Extract PCX seg to d14
; Copy to address reg
Application Hints
Rel. 1.3, 18.12.2009
Errata Sheet