KIT_TC1797_SK Infineon Technologies, KIT_TC1797_SK Datasheet - Page 34

• Manufacturer Part Number: KIT_TC1797_SK
• Description: KIT STARTER AUDO FUTURE TC1797
• Manufacturer: Infineon Technologies
• Series: Audo Futurer
• Type: MCUr

Specifications of KIT_TC1797_SK

• Contents: Board, Adapters, Cables, CD, Power Supply
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: TC1797
• Other names: KITTC1797SKIN

by LMB masters in the 2KByte DCache configuration, this would affect
debuggers. Hence it would only be possible to view this memory space in a
debugger if it takes appropriate steps to make the memory region accessable
(e.g. by temporarily setting the DCache size to 0KByte) to examine that address
range.
DMI_TC.016 CPU Deadlock possible when Cacheable access encounters
Flash Double-Bit Error
A problem exists whereby the TriCore CPU may become deadlocked when
attempting a mis-aligned load access to a cacheable address. The problem will
be triggered in the following situation:
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It should be noted that under normal operation, LMB block transfers will not
result in a bus error condition being flagged on the second beat of a block
transfer. However, such a condition may be encountered when accessing the
on-chip Flash, if the second double-word of data accessed from the Flash (for
the second half of the cache line) contains an uncorrectable double-bit error.
When this condition is triggered, the first part of the requested data is obtained
from the valid first beat of the BTR2 transfer, and the second part is required
from the errored second beat. In this case, no error is flagged to the TriCore
CPU and the transaction is incorrectly re-started on the LMB. In the case of a
Flash double-bit error, this transaction will be re-tried continuously on the LMB
TC1797, EES-AC, ES-AC, AC
The TriCore CPU executes a load instruction whose target address is not
naturally aligned - a data word access which targets an address which is not
word aligned, or a data / address double-word access which is not double-
word aligned.
The mis-aligned load access targets a cacheable address, whether the
device is configured with a data cache or not.
The mis-aligned load access spans two halves of the same 128-bit cache
line. For instance, a data word access with address offset 6
The mis-aligned load access results in a cache miss, which will refill the 128-
bit cache line / Data Line Buffer (DLB) via a Block Transfer 2 (BTR2) read
transaction on the LMB, and this LMB read encounters a bus error condition
in the second beat of the block transfer.
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Functional Deviations
Rel. 1.3, 18.12.2009
H
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Errata Sheet