LAXP2-17E-5FTN256E Lattice, LAXP2-17E-5FTN256E Datasheet - Page 15

• Manufacturer Part Number: LAXP2-17E-5FTN256E
• Description: IC FPGA AUTO 17K LUTS 256-BGA
• Manufacturer: Lattice

Specifications of LAXP2-17E-5FTN256E

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Primary Clock Routing
The clock routing structure in LA-LatticeXP2 devices consists of a network of eight primary clock lines (CLK0
through CLK7) per quadrant. The primary clocks of each quadrant are generated from muxes located in the center
of the device. All the clock sources are connected to these muxes. Figure 2-9 shows the clock routing for one quad-
rant. Each quadrant mux is identical. If desired, any clock can be routed globally.
Figure 2-9. Per Quadrant Primary Clock Selection
Dynamic Clock Select (DCS)
The DCS is a smart multiplexer function available in the primary clock routing. It switches between two independent
input clock sources without any glitches or runt pulses. This is achieved irrespective of when the select signal is
toggled. There are two DCS blocks per quadrant; in total, eight DCS blocks per device. The inputs to the DCS block
come from the center muxes. The output of the DCS is connected to primary clocks CLK6 and CLK7 (see Figure 2-
9).
Figure 2-10 shows the timing waveforms of the default DCS operating mode. The DCS block can be programmed
to other modes. For more information on the DCS, see TN1126,
Guide.
Figure 2-10. DCS Waveforms
Secondary Clock/Control Routing
Secondary clocks in the LA-LatticeXP2 devices are region-based resources. The benefit of region-based
resources is the relatively low injection delay and skew within the region, as compared to primary clocks. EBR
rows, DSP rows and a special vertical routing channel bound the secondary clock regions. This special vertical
routing channel aligns with either the left edge of the center DSP block in the DSP row or the center of the DSP
row. Figure 2-11 shows this special vertical routing channel and the six secondary clock regions for the LA-
CLK0
30:1
SEL
CLK1
CLK0
DCSOUT
CLK1
30:1
CLK2
30:1
Primary Clock Sources: PLLs + CLKDIVs + PIOs + Routing
8 Primary Clocks (CLK0 to CLK7) per Quadrant
CLK3
30:1
CLK4
30:1
2-12
CLK5
30:1
LatticeXP2 sysCLOCK PLL Design and Usage
29:1
CLK6
LA-LatticeXP2 Family Data Sheet
DCS
29:1
29:1
CLK7
DCS
29:1
Architecture