LAXP2-17E-5FTN256E Lattice, LAXP2-17E-5FTN256E Datasheet - Page 61

• Manufacturer Part Number: LAXP2-17E-5FTN256E
• Description: IC FPGA AUTO 17K LUTS 256-BGA
• Manufacturer: Lattice

Specifications of LAXP2-17E-5FTN256E

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
LA-LatticeXP2 External Switching Characteristics (Continued)
t
t
t
DDR
t
t
t
t
f
f
Primary Clock
f
t
t
Edge Clock (ECLK1 and ECLK2)
f
t
t
1. General timing numbers based on LVCMOS 2.5, 12mA, 0pf load.
2. DDR timing numbers based on SSTL25.
3. DDR2 timing numbers based on SSTL18.
Timing v. A 0.12
HPLL
SU_DELPLL
H_DELPLL
DVADQ
DVEDQ
DQVBS
DQVAS
MAX_DDR
MAX_DDR2
MAX_PRI
W_PRI
SKEW_PRI
MAX_ECLK
W_ECLK
SKEW_ECLK
Parameter
2
and DDR2
3
I/O Pin Parameters
Clock to Data Hold - PIO Input Register
Clock to Data Setup - PIO Input Register with Data Input Delay
Clock to Data Hold - PIO Input Register with Input Data Delay
Data Valid After DQS (DDR Read)
Data Hold After DQS (DDR Read)
Data Valid Before DQS
Data Valid After DQS
DDR Clock Frequency
DDR Clock Frequency
Frequency for Primary Clock Tree
Clock Pulse Width for Primary Clock
Primary Clock Skew Within a Bank
Frequency for Edge Clock
Clock Pulse Width for Edge Clock
Edge Clock Skew Within an Edge of the Device
Over Recommended Operating Conditions
Description
3-17
DC and Switching Characteristics
LA-LatticeXP2 Family Data Sheet
LA-XP2-5
LA-XP2-8
LA-XP2-17
LA-XP2-5
LA-XP2-8
LA-XP2-17
LA-XP2-5
LA-XP2-8
LA-XP2-17
LA-XP2
LA-XP2
LA-XP2
LA-XP2
LA-XP2
LA-XP2
LA-XP2
LA-XP2
LA-XP2
LA-XP2
LA-XP2
LA-XP2
Device
Min.
1.32
1.32
1.32
2.16
2.18
2.14
0.00
0.00
0.00
0.71
0.25
0.25
133
95
—
—
—
—
—
1
1
-5
Max.
0.29
133
166
311
160
311
130
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Units
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
UI
UI
UI
UI
ns
ps
ns
ps