LAXP2-17E-5FTN256E Lattice, LAXP2-17E-5FTN256E Datasheet - Page 38

• Manufacturer Part Number: LAXP2-17E-5FTN256E
• Description: IC FPGA AUTO 17K LUTS 256-BGA
• Manufacturer: Lattice

Specifications of LAXP2-17E-5FTN256E

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
LA-LatticeXP2 devices contain two types of sysIO buffer pairs.
1. Top and Bottom (Banks 0, 1, 4 and 5) sysIO Buffer Pairs (Single-Ended Outputs Only)
2. Left and Right (Banks 2, 3, 6 and 7) sysIO Buffer Pairs (50% Differential and 100% Single-Ended Outputs)
Typical sysIO I/O Behavior During Power-up
The internal power-on-reset (POR) signal is deactivated when V
After the POR signal is deactivated, the FPGA core logic becomes active. It is the user’s responsibility to ensure
that all other V
I/O banks that are critical to the application. For more information on controlling the output logic state with valid
input logic levels during power-up in LA-LatticeXP2 devices, see TN1136,
The V
fers. In order to simplify system design while providing consistent and predictable I/O behavior, it is recommended
that the I/O buffers be powered-up prior to the FPGA core fabric. V
together with the V
Supported sysIO Standards
The LA-LatticeXP2 sysIO buffer supports both single-ended and differential standards. Single-ended standards
can be further subdivided into LVCMOS, LVTTL and other standards. The buffers support the LVTTL, LVCMOS
1.2V, 1.5V, 1.8V, 2.5V and 3.3V standards. In the LVCMOS and LVTTL modes, the buffer has individual configu-
ration options for drive strength, bus maintenance (weak pull-up, weak pull-down, or a bus-keeper latch) and
open drain. Other single-ended standards supported include SSTL and HSTL. Differential standards supported
include LVDS, MLVDS, BLVDS, LVPECL, RSDS, differential SSTL and differential HSTL. Tables 2-12 and 2-13
show the I/O standards (together with their supply and reference voltages) supported by LA-LatticeXP2 devices.
For further information on utilizing the sysIO buffer to support a variety of standards, see TN1136,
sysIO Usage
The sysIO buffer pairs in the top banks of the device consist of two single-ended output drivers and two sets of
single-ended input buffers (both ratioed and referenced). One of the referenced input buffers can also be con-
figured as a differential input. 

The two pads in the pair are described as “true” and “comp”, where the true pad is associated with the positive
side of the differential input buffer and the comp (complementary) pad is associated with the negative side of
the differential input buffer. 

Only the I/Os on the top and bottom banks have programmable PCI clamps.
The sysIO buffer pairs in the left and right banks of the device consist of two single-ended output drivers, two
sets of single-ended input buffers (both ratioed and referenced) and one differential output driver. One of the ref-
erenced input buffers can also be configured as a differential input. 

The two pads in the pair are described as “true” and “comp”, where the true pad is associated with the positive
side of the differential I/O, and the comp pad is associated with the negative side of the differential I/O. 

LVDS differential output drivers are available on 50% of the buffer pairs on the left and right banks.
CC
and V
Guide.
CCIO
CCAUX
CC
banks are active with valid input logic levels to properly control the output logic states of all the
supply the power to the FPGA core fabric, whereas the V
and V
CCAUX
supplies.
2-35
CC
CCIO
and V
LA-LatticeXP2 Family Data Sheet
supplies should be powered-up before or
LatticeXP2 sysIO Usage
CCAUX
CCIO
have reached satisfactory levels.
supplies power to the I/O buf-
Architecture
Guide.
LatticeXP2