LAXP2-17E-5FTN256E Lattice, LAXP2-17E-5FTN256E Datasheet - Page 55

• Manufacturer Part Number: LAXP2-17E-5FTN256E
• Description: IC FPGA AUTO 17K LUTS 256-BGA
• Manufacturer: Lattice

Specifications of LAXP2-17E-5FTN256E

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
LVPECL
The LA-LatticeXP2 devices support the differential LVPECL standard. This standard is emulated using comple-
mentary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The LVPECL input stan-
dard is supported by the LVDS differential input buffer. The scheme shown in Figure 3-3 is one possible solution for
point-to-point signals.
Figure 3-3. Differential LVPECL
Table 3-3. LVPECL DC Conditions
16mA
16mA
V
V
V
Z
R
R
R
V
V
V
V
Z
I
1. For input buffer, see LVDS table.
DC
CCIO
CCIO
OUT
OH
OL
OD
BACK
CCIO
T
CM
S
P
Parameter
(+/-5%)
(+/-5%)
On-chip
= 3.3V
= 3.3V
R
R
Over Recommended Operating Conditions
Output Driver Supply (+/-5%)
Driver Impedance
Driver Series Resistor (+/-1%)
Driver Parallel Resistor (+/-1%)
Receiver Termination (+/-1%)
Output High Voltage (After R
Output Low Voltage (After R
Output Differential Voltage (After R
Output Common Mode Voltage
Back Impedance
DC Output Current
S
S
1
Off-chip
= 93.1 ohms
= 93.1 ohms
(+/-1%)
(+/-1%)
Description
Zo = 100 ohm differential
R
P
Transmission line,
= 196 ohms
(+/-1%)
3-11
P
P
)
)
P
)
R
T
= 100 ohms
DC and Switching Characteristics
(+/-1%)
LA-LatticeXP2 Family Data Sheet
Typical
12.11
100.5
3.30
2.05
1.25
0.80
1.65
196
100
10
93
Off-chip
Units
mA
¾
¾
¾
¾
¾
V
V
V
V
V
On-chip
+
-