LAXP2-17E-5FTN256E Lattice, LAXP2-17E-5FTN256E Datasheet - Page 43

• Manufacturer Part Number: LAXP2-17E-5FTN256E
• Description: IC FPGA AUTO 17K LUTS 256-BGA
• Manufacturer: Lattice

Specifications of LAXP2-17E-5FTN256E

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
4. For more information on device configuration, see TN1141,
Soft Error Detect (SED) Support
LA-LatticeXP2 devices have dedicated logic to perform Cyclic Redundancy Code (CRC) checks. During configura-
tion, the configuration data bitstream can be checked with the CRC logic block. In addition, LA-LatticeXP2 devices
can be programmed for checking soft errors in SRAM. The SED operation can run in the background during user
mode (normal operation). In the event a soft error occurs, the device can be programmed to either reload from a
known good boot image (from internal Flash or external SPI memory) or generate an error signal.
For further information on SED support, see TN1130,
On-Chip Oscillator
Every LA-LatticeXP2 device has an internal CMOS oscillator that is used to derive a Master Clock (CCLK) for con-
figuration. The oscillator and CCLK run continuously and are available to user logic after configuration is complete.
The available CCLK frequencies are listed in Table 2-14. When a different CCLK frequency is selected during the
design process, the following sequence takes place:
1. Device powers up with the default CCLK frequency.
2. During configuration, users select a different CCLK frequency.
3. CCLK frequency changes to the selected frequency after clock configuration bits are received.
This internal CMOS oscillator is available to the user by routing it as an input clock to the clock tree. For further
information on the use of this oscillator for configuration or user mode, see TN1141,
Guide.
Table 2-14. Selectable CCLKs and Oscillator Frequencies During Configuration and User Mode
to the original backup configuration and try again. This all can be done without power cycling the system. For
more information please see TN1220,
1. Software default oscillator frequency.
2. Software default CCLK frequency.
3. Frequency not valid for CCLK.
LatticeXP2 Dual Boot
CCLK/Oscillator (MHz)
LatticeXP2 Soft Error Detection (SED) Usage
2-40
163
2.5
3.1
80
4.3
5.4
6.9
8.1
9.2
10
13
15
20
26
32
40
54
3
1
2
3
LatticeXP2 sysCONFIG Usage
Feature.
LA-LatticeXP2 Family Data Sheet
LatticeXP2 sysCONFIG Usage
Guide.
Architecture
Guide.