LAXP2-17E-5FTN256E Lattice, LAXP2-17E-5FTN256E Datasheet - Page 2

• Manufacturer Part Number: LAXP2-17E-5FTN256E
• Description: IC FPGA AUTO 17K LUTS 256-BGA
• Manufacturer: Lattice

Specifications of LAXP2-17E-5FTN256E

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

May 2009
Features
Table 1-1. LA-LatticeXP2 Family Selection Guide
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or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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Device
LUTs (K)
Distributed RAM (KBits)
EBR SRAM (KBits)
EBR SRAM Blocks
sysDSP Blocks
18 x 18 Multipliers
V
GPLL
Max Available I/O
Packages and I/O Combinations
132-Ball csBGA (8x8 mm)
144-Pin TQFP (20 x 20 mm)
208-Pin PQFP (28 x 28 mm)
256-Ball ftBGA (17 x17 mm)
CC
flexiFLASH™ Architecture
AEC-Q100 Tested and Qualified
Live Update Technology
sysDSP™ Block
Embedded and Distributed Memory
sysCLOCK™ PLLs
Voltage
• Instant-on
• Infinitely reconfigurable
• Single chip
• FlashBAK™ technology
• Serial TAG memory
• Design security
• TransFR™ technology
• Secure updates with 128 bit AES encryption
• Dual-boot with external SPI
• Three to five blocks for high performance 
• 12 to 20 18x18 multipliers
• Each block supports one 36x36 multiplier or four
• Up to 276 Kbits sysMEM™ EBR
• Up to 35 Kbits Distributed RAM
• Up to four analog PLLs per device
• Clock multiply, divide and phase shifting
Multiply and Accumulate
18x18 or eight 9x9 multipliers
LA-XP2-5
LA-LatticeXP2 Family Data Sheet
166
172
100
146
1.2
172
10
12
86
5
9
3
2
1-1
Flexible I/O Buffer
Pre-engineered Source Synchronous
Interfaces
Density And Package Options
Flexible Device Configuration
System Level Support
• sysIO™ buffer supports:
• DDR / DDR2 interfaces up to 200 MHz
• 7:1 LVDS interfaces support display applications
• XGMII
• 5k to 17k LUT4s, 86 to 358 I/Os
• csBGA, ftBGA, TQFP and PQFP packages
• Density migration supported
• SPI (master and slave) Boot Flash Interface
• Dual Boot Image supported
• Soft Error Detect (SED) macro embedded
• IEEE 1149.1 and IEEE 1532 Compliant
• On-chip oscillator for initialization & general use
• Devices operate with 1.2V power supply
– LVCMOS 33/25/18/15/12; LVTTL
– SSTL 33/25/18 class I, II
– HSTL15 class I; HSTL18 class I, II
– PCI
– LVDS, Bus-LVDS, MLVDS, LVPECL, RSDS
LA-XP2-8
221
201
100
146
201
1.2
18
12
16
86
8
4
2
Introduction
DS1024
LA-XP2-17
Data Sheet DS1024
Introduction_01.1
276
201
146
201
1.2
17
35
15
20
5
4