LAXP2-17E-5FTN256E Lattice, LAXP2-17E-5FTN256E Datasheet - Page 62

• Manufacturer Part Number: LAXP2-17E-5FTN256E
• Description: IC FPGA AUTO 17K LUTS 256-BGA
• Manufacturer: Lattice

Specifications of LAXP2-17E-5FTN256E

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
LA-LatticeXP2 Internal Switching Characteristics
PFU/PFF Logic Mode Timing
t
t
t
t
t
t
t
t
t
t
PFU Dual Port Memory Mode Timing
t
t
t
t
t
t
t
PIO Input/Output Buffer Timing
t
t
IOLOGIC Input/Output Timing
t
t
t
t
t
t
t
t
t
t
EBR Timing
t
t
t
t
t
t
t
LUT4_PFU
LUT6_PFU
LSR_PFU
SUM_PFU
HM_PFU
SUD_PFU
HD_PFU
CK2Q_PFU
RSTREC_PFU
RST_PFU
CORAM_PFU
SUDATA_PFU
HDATA_PFU
SUADDR_PFU
HADDR_PFU
SUWREN_PFU
HWREN_PFU
IN_PIO
OUT_PIO
SUI_PIO
HI_PIO
COO_PIO
SUCE_PIO
HCE_PIO
SULSR_PIO
HLSR_PIO
RSTREC_PIO
RST_PIO
DEL
CO_EBR
COO_EBR
SUDATA_EBR
HDATA_EBR
SUADDR_EBR
HADDR_EBR
SUWREN_EBR
Parameter
LUT4 delay (A to D inputs to F output)
LUT6 delay (A to D inputs to OFX output)
Set/Reset to output of PFU (Asynchronous)
Clock to Mux (M0,M1) Input Setup Time
Clock to Mux (M0,M1) Input Hold Time
Clock to D input setup time
Clock to D input hold time
Clock to Q delay, (D-type Register Configuration)
Asynchronous reset recovery time for PFU Logic
Asynchronous reset time for PFU Logic
Clock to Output (F Port)
Data Setup Time
Data Hold Time
Address Setup Time
Address Hold Time
Write/Read Enable Setup Time
Write/Read Enable Hold Time
Input Buffer Delay (LVCMOS25)
Output Buffer Delay (LVCMOS25)
Input Register Setup Time (Data Before Clock)
Input Register Hold Time (Data after Clock)
Output Register Clock to Output Delay
Input Register Clock Enable Setup Time
Input Register Clock Enable Hold Time
Set/Reset Setup Time
Set/Reset Hold Time
Asynchronous reset recovery time for IO Logic
Asynchronous reset time for PFU Logic
Dynamic Delay Step Size
Clock (Read) to Output from Address or Data
Clock (Write) to Output from EBR Output Register
Setup Data to EBR Memory (Write Clk)
Hold Data to EBR Memory (Write Clk)
Setup Address to EBR Memory (Write Clk)
Hold Address to EBR Memory (Write Clk)
Setup Write/Read Enable to EBR Memory (Write/Read Clk)
Over Recommended Operating Conditions
Description
3-18
DC and Switching Characteristics
LA-LatticeXP2 Family Data Sheet
1
-0.056
-0.290
-0.392
-0.204
-0.028
-0.094
-0.232
-0.159
-0.184
0.156
0.098
0.003
0.330
0.392
0.219
1.215
0.448
0.041
0.220
0.269
0.035
0.270
0.209
Min.
—
—
—
—
—
—
—
—
—
—
—
—
—
-5
0.522
0.865
0.405
0.791
0.865
1.535
0.708
0.724
0.457
3.552
0.275
1.308
0.035
0.461
Max.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns