LAXP2-17E-5FTN256E Lattice, LAXP2-17E-5FTN256E Datasheet - Page 18

• Manufacturer Part Number: LAXP2-17E-5FTN256E
• Description: IC FPGA AUTO 17K LUTS 256-BGA
• Manufacturer: Lattice

Specifications of LAXP2-17E-5FTN256E

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 2-15. Edge Clock Mux Connections
sysMEM Memory
LA-LatticeXP2 devices contains a number of sysMEM Embedded Block RAM (EBR). The EBR consists of 18 Kbit
RAM with dedicated input and output registers.
sysMEM Memory Block
The sysMEM block can implement single port, dual port or pseudo dual port memories. Each block can be used in
a variety of depths and widths as shown in Table 2-5. FIFOs can be implemented in sysMEM EBR blocks by using
support logic with PFUs. The EBR block supports an optional parity bit for each data byte to facilitate parity check-
ing. EBR blocks provide byte-enable support for configurations with18-bit and 36-bit data widths.
GPLL Output CLKOP
GPLL Output CLKOS
Clock Input Pad
GPLL Input Pad
GPLL Input Pad
Input Pad
Input Pad
Routing
Routing
Routing
2-15
Top and Bottom
ECLK1/ ECLK2
Left and Right
Left and Right
(Both Muxes)
Edge Clocks
Edge Clocks
Edge Clocks
LA-LatticeXP2 Family Data Sheet
ECLK1
ECLK2
Architecture