PC28F512P30EFA Micron Technology Inc, PC28F512P30EFA Datasheet - Page 16

• Manufacturer Part Number: PC28F512P30EFA
• Manufacturer: Micron Technology Inc

Specifications of PC28F512P30EFA

• Cell Type: NOR
• Density: 512Mb
• Interface Type: Parallel/Serial
• Address Bus: 25b
• Operating Supply Voltage (typ): 1.8V
• Operating Temp Range: -40C to 85C
• Package Type: BGA
• Program/erase Volt (typ): 8.5 to 9.5V
• Sync/async: Async/Sync
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 1.7V
• Operating Supply Voltage (max): 2V
• Word Size: 16b
• Number Of Words: 32M
• Supply Current: 31mA
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / Rohs Status: Compliant

5.0
Table 5:
5.1
Note:
5.2
Datasheet
16
Read
Write
Output Disable
Standby
Reset
Notes:
1.
2.
3.
Bus Operation
Asynchronous
Synchronous
Refer to the
operation.
X = Don’t Care (H or L).
RST# must be at V
Bus Operations Summary
Bus Operations
CE# low and RST# high enable device read operations. The device internally decodes
upper address inputs to determine the accessed block. ADV# low opens the internal
address latches. OE# low activates the outputs and gates selected data onto the I/O
bus.
Bus cycles to/from the P30-65nm device conform to standard microprocessor bus
operations.
the logic levels that must be applied to the device control signal inputs.
Read - Asynchronous Single Word Mode
To perform an asynchronous single word read, an address is driven onto the address
bus, and CE# is asserted. ADV# must be held low throughout the read cycle for TSOP
package. ADV# can either be driven high to latch the address or be held low
throughout the read cycle for Easy BGA package. WE# and RST# must already have
been deasserted. WAIT is set to a deasserted state during single word mode as
determined by RCR.10. CLK is not used for asynchronous single word reads, and is
ignored. After OE# is asserted, the data is driven onto DQ[15:0] after an initial access
time t
If only asynchronous reads are to be performed, CLK should be tied to a valid
V
Refer to the following waveforms for more detailed information.
“Asynchronous Single-Word Read (ADV# Low)” on page
“Asynchronous Single-Word Read for Easy BGA (ADV# Latch)” on page
Read - Asynchronous Page Mode
To perform an asynchronous page read, an address is driven onto the address bus, and
CE# and ADV# are asserted. WE# and RST# must already have been deasserted.
WAIT is set to a deasserted state during asynchronous page mode and single word
mode as determined by RCR.10. ADV# can be driven high to latch the address, or it
must be held low throughout the read cycle. CLK is not used for asynchronous page-
mode reads, and is ignored. After OE# is asserted, the data is driven onto DQ[15:0]
after an initial access time t
-” on page
IH
Table 7, “Command Bus Cycles” on page 21
level, WAIT signal can be floated and ADV# must be tied to ground.
AVQV
RST#
SS
V
V
V
V
V
V
IH
IH
IH
IH
IH
IL
± 0.2V to meet the maximum specified power-down current.
or t
51.)
Table 5, “Bus Operations Summary”
GLQV
Running
CLK
X
X
X
X
X
delay. (See
ADV#
X
X
X
L
L
L
AVQV
Table 25, “AC Read Specifications -” on page
or t
CE#
H
L
L
X
L
L
GLQV
delay. (See
OE#
H
H
X
X
L
L
for valid DQ[15:0] during a write
summarizes the bus operations and
(Easy
WE#
Table 25, “AC Read Specifications
H
H
H
X
X
L
52, and
BGA)
Deasserted
High-Z
High-Z
High-Z
High-Z
Driven
WAIT
Figure 18,
Figure 19,
Order Number: 208042-05
DQ[15:0]
53.
Output
Output
High-Z
High-Z
High-Z
Input
51).
P30-65nm
Apr 2010
Notes
2,3
1
2
2
-
-