PC28F512P30EFA Micron Technology Inc, PC28F512P30EFA Datasheet - Page 23

• Manufacturer Part Number: PC28F512P30EFA
• Manufacturer: Micron Technology Inc

Specifications of PC28F512P30EFA

• Cell Type: NOR
• Density: 512Mb
• Interface Type: Parallel/Serial
• Address Bus: 25b
• Operating Supply Voltage (typ): 1.8V
• Operating Temp Range: -40C to 85C
• Package Type: BGA
• Program/erase Volt (typ): 8.5 to 9.5V
• Sync/async: Async/Sync
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 1.7V
• Operating Supply Voltage (max): 2V
• Word Size: 16b
• Number Of Words: 32M
• Supply Current: 31mA
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / Rohs Status: Compliant

P30-65nm
Table 8:
Table 9:
7.3
7.4
7.5
Datasheet
23
Lock Register 1
128-bit User-Programmable OTP registers
Notes:
1.
2.
3.
Note:
ID Code Type
BBA = Block Base Address.
DBA = Device base Address, Numonyx reserves other configuration address locations.
The GPR is used as read out register for Extended Function Interface command.
Device Code
The 2-Gbit devices do not have a unique Device ID associated with them. Each die within the stack can be identified by
either of the 1-Gbit Device ID codes depending on its configuration.
Device Identifier Information (Sheet 2 of 2)
Device ID codes
Read CFI
The Read CFI command instructs the device to output Common Flash Interface data
when read. See
“Common Flash Interface” on page 61
within the CFI database.
Read Status Register
To read the Status Register, issue the Read Status Register command at any address.
Status Register information is available to which the Read Status Register, Word
Program, or Block Erase command was issued. SRD is automatically made available
following a Word Program, Block Erase, or Block Lock command sequence. Reads from
the device after any of these command sequences outputs the device’s status until
another valid command is written (e.g. the Read Array command).
The Status Register is read using single asynchronous-mode or synchronous burst
mode reads. SRD is output on DQ[7:0], while 0x00 is output on DQ[15:8]. In
asynchronous mode the falling edge of OE#, or CE# (whichever occurs first) updates
and latches the Status Register contents. However, when reading the Status Register in
synchronous burst mode, CE# or ADV# must be toggled to update SRD.
The Device Write Status bit (SR.7) provides overall status of the device. SR[6:1]
present status and error information about the program, erase, suspend, VPP, and
block-locked operations.
See
Register.
Clear Status Register
The Clear Status Register command clears the Status Register. It functions independent
of VPP. The WSM sets and clears SR[7], but it sets bits SR[5:3,1] without clearing
them. The Status Register should be cleared before starting a command sequence to
avoid any ambiguity. A device reset also clears the Status Register.
Table 12, “Status Register Description” on page 34
Item
512-Mbit
Density
Device
1-Gbit
Figure 6.1, “Device Command Codes” on page
(Top Parameter)
8960
8962
-T
shows CFI information and address offsets
Address
0x8A–0x109
0x89
Device Identifier Codes
(Bottom Parameter)
(1,2)
8961
8963
-B
for the description of the Status
PR-LK1 OTP Register lock data
User OTP Register data
19.
(Symmetrical Blocks)
Data(x16)
Order Number:208042-05
Section A.1,
899A
8999
-E
Apr 2010