UPD78F0988AGC-8BS Renesas Electronics America, UPD78F0988AGC-8BS Datasheet - Page 248

• Manufacturer Part Number: UPD78F0988AGC-8BS
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0988AGC-8BS

• Lead Free Status / Rohs Status: Supplier Unconfirmed

246
Figure 12-14. Timing of Asynchronous Serial Interface Reception Completion Interrupt Request Generation
RxD0n (Input)
(d) Reception
INTSRn
When the RXE0n bit of asynchronous serial interface mode register n (ASIM0n) is set (1), a receive
operation is enabled and sampling of the RxD0n pin input is performed.
RxD0n pin input sampling is performed using the serial clock specified by ASIM0n.
When the RxD0n pin input becomes low, the 5-bit counter of the baud rate generator starts counting, and
at the time when half the time determined by the specified baud rate has passed, the data sampling start
timing signal is output. If the RxD0n pin input sampled again as a result of this start timing signal is low,
it is identified as a start bit, the 5-bit counter is initialized and starts counting, and data sampling is
performed. When character data, a parity bit and one stop bit are detected after the start bit, reception
of one frame of data ends.
When one frame of data has been received, the receive data in the shift register is transferred to receive
buffer register n (RXB0n), and a reception completion interrupt request (INTSRn) is generated.
If an error occurs, the receive data in which the error occurred is still transferred to RXB0n.
INTSRn is generated if bit 1 (ISRM0n) of ASIM0n is cleared (0) on occurrence of the error.
If the ISRM0n bit is set (1), INTSRn is not generated.
If the RXE0n bit is reset (0) during the receive operation, the receive operation is stopped immediately.
In this case, the contents of RXB0n and ASIS0n are not changed, and INTSRn and INTSER0 are not
generated.
Caution Receive buffer register n (RXB0n) must be read even if a receive error occurs. If RXB0n
Remark n = 0, 1
is not read, an overrun error will occur when the next data is received, and the receive
error state will continue indefinitely.
CHAPTER 12 SERIAL INTERFACES UART00 AND UART01
START
D0
User’s Manual U13029EJ7V1UD
D1
D2
D6
D7
Parity
STOP