UPD78F0988AGC-8BS Renesas Electronics America, UPD78F0988AGC-8BS Datasheet - Page 355

• Manufacturer Part Number: UPD78F0988AGC-8BS
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0988AGC-8BS

• Lead Free Status / Rohs Status: Supplier Unconfirmed

19.3 Instruction List by Addressing
Conditional
branch
CPU
control
Instruction
Group
Notes 1. When the internal high-speed RAM area is accessed or when an instruction that does not access data
Remarks 1. One clock of an instruction is equal to one CPU clock (f
(1) 8-bit instructions
MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC,
ROLC, ROR4, ROL4, PUSH, POP, DBNZ
2. When an area other than the internal high-speed RAM area is accessed
Mnemonic
BTCLR
DBNZ
SEL
NOP
EI
DI
HALT
STOP
2. The number of clocks shown is when the program is stored in the internal ROM area.
3. n indicates the number of wait states when the external memory expansion area is read.
4. m indicates the number of wait states when the external memory expansion area is written.
is executed
register (PCC).
saddr.bit, $addr16
sfr.bit, $addr16
A.bit, $addr16
PSW.bit, $addr16
[HL].bit, $addr16
B, $addr16
C, $addr16
saddr, $addr16
RBn
Operand
CHAPTER 19 INSTRUCTION SET
User’s Manual U13029EJ7V1UD
Byte
4
4
3
4
3
2
2
3
2
1
2
2
2
2
Note 1 Note 2
10
10
–
8
–
6
6
8
4
2
–
–
6
6
Clock
12 + n + m
12
12
12
10
–
–
–
–
–
6
6
–
–
PC
then reset (saddr.bit)
PC
then reset sfr.bit
PC
then reset A.bit
PC
then reset PSW.bit
PC
then reset (HL).bit
B
PC
C
PC
(saddr)
PC
RBS1, 0
No operation
IE
IE
Set HALT mode
Set STOP mode
B – 1, then
C – 1, then
1 (Enable interrupt)
0 (Disable interrupt)
PC + 4 + jdisp8 if (saddr.bit) = 1
PC + 4 + jdisp8 if sfr.bit = 1
PC + 3 + jdisp8 if A.bit = 1
PC + 4 + jdisp8 if PSW.bit = 1
PC + 3 + jdisp8 if (HL).bit = 1
PC + 2 + jdisp8 if B
PC + 2 + jdisp8 if C
PC + 3 + jdisp8 if (saddr)
CPU
) selected by the processor clock control
(saddr) – 1, then
n
Operation
0
0
0
Z AC CY
Flag
353