UPD78F0988AGC-8BS Renesas Electronics America, UPD78F0988AGC-8BS Datasheet - Page 352

• Manufacturer Part Number: UPD78F0988AGC-8BS
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0988AGC-8BS

• Lead Free Status / Rohs Status: Supplier Unconfirmed

350
Instruction
BCD
adjustment
Bit
manipulation
Group
Notes 1. When the internal high-speed RAM area is accessed or when an instruction that does not access data
Remarks 1. One clock of an instruction is equal to one CPU clock (f
2. When an area other than the internal high-speed RAM area is accessed
Mnemonic
ADJBA
ADJBS
MOV1
AND1
OR1
XOR1
2. The number of clocks shown is when the program is stored in the internal ROM area.
3. n indicates the number of wait states when the external memory expansion area is read.
4. m indicates the number of wait states when the external memory expansion area is written.
is executed
register (PCC).
CY, saddr.bit
CY, sfr.bit
CY, A.bit
CY, PSW.bit
CY, [HL].bit
saddr.bit, CY
sfr.bit, CY
A.bit, CY
PSW.bit, CY
[HL].bit, CY
CY, saddr.bit
CY, sfr.bit
CY, A.bit
CY, PSW.bit
CY, [HL].bit
CY, saddr.bit
CY, sfr.bit
CY, A.bit
CY, PSW.bit
CY, [HL].bit
CY, saddr.bit
CY, sfr.bit
CY, A.bit
CY, PSW.bit
CY, [HL].bit
Operand
CHAPTER 19 INSTRUCTION SET
User’s Manual U13029EJ7V1UD
Byte
2
2
3
3
2
3
2
3
3
2
3
2
3
3
2
3
2
3
3
2
3
2
3
3
2
3
2
Note 1 Note 2
4
4
6
–
4
–
6
6
–
4
–
6
6
–
4
–
6
6
–
4
–
6
6
–
4
–
6
Clock
8 + n + m
7 + n
7 + n
7 + n
7 + n
–
–
7
7
–
7
8
8
–
8
7
7
–
7
7
7
–
7
7
7
–
7
Decimal Adjust Accumulator after
Addition
Decimal Adjust Accumulator after
Subtract
CY
CY
CY
CY
CY
(saddr.bit)
sfr.bit
A.bit
PSW.bit
(HL).bit
CY
CY
CY
CY
CY
CY
CY
CY
CY
CY
CY
CY
CY
CY
CY
(saddr.bit)
sfr.bit
A.bit
PSW.bit
(HL).bit
CY (saddr.bit)
CY sfr.bit
CY A.bit
CY PSW.bit
CY (HL).bit
CY (saddr.bit)
CY sfr.bit
CY A.bit
CY PSW.bit
CY (HL).bit
CY
CY
CY
CY
CY
CPU
CY
CY
) selected by the processor clock control
CY
CY
(saddr.bit)
sfr.bit
A.bit
PSW.bit
(HL).bit
CY
Operation
Z AC CY
Flag